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參數(shù)資料
| 型號： | ICS2002Y |
| 元件分類： | Codec |
| 英文描述： | Wavedec Digital Audio Codec |
| 中文描述： | Wavedec數(shù)字音頻編解碼器 |
| 文件頁數(shù)： | 16/21頁 |
| 文件大?。?/td> | 550K |
| 代理商： | ICS2002Y |
IR92 reserved
IR93 reserved
IR94 DSP Control/Status (DSPCS)
Bits 7:4 - Index Counter Value (Read Only)
This value indicates the current contents of the DSP
address Index Counter, and is provided as a code debug
aid for use in Step Mode. In normal operation it should
be ignored. It is reset to zero when the DSP is not
running, and increments by one at the completion of
each “pass” of the DSP engine.
Bit 3 - DSP Sequence Complete (Read only)
This bit is set each time the DSP completes its sequence
and restarts. It is reset to zero when the DSPRUN bit is
zero or after a read of this register.
Bit 2 - DSP Output Saturation Detect
This bit is set to one whenever the DSP output value
written to any output destination (DATA RAM, DAC,
or Record FIFO) exceeds a sixteen bit signed range. In
these cases, the DSP output saturates to $7FFF or $8000
(for positive or negative values) rather than overflow-
ing. It is reset to zero when the DSPRUN bit is zero or
after a read of this register.
Bit 1 - DSP Step Mode
This bit is intended as a DSP code debug aid only.
When set to a one, this bit halts the DSP microcode
sequencer at the end of each “pass” of code. This
enables the host to read the DATA RAM contents to
check the results of the previous calculations. Note that
writes to the Record FIFO and DAC will be captured
by the DATA RAM “under” them to aid with debug
efforts. For normal operation, this bit
MUST
be set to
a zero.
Bit 0 - DSP Run
When written to one, this bit starts the DSP engine
running. A zero stops and resets the DSP engine execu-
tion. This bit is reset by MCR.
Before running the DSP, the Code and Data RAMs must be
loaded. To do this, perform the following:
1) write 95h (DSPRA) to the desired address
2) write 96h (Code Ram data) or 97h (Data RAM data) to the
desired 16-bit value.
3) repeat 1 and 2 for all RAM locations of both RAMs.
4) when done, write any data to DSPRA to reset the load logic.
ICS will provide algorithm and constants data supporting fil-
tering functions for various sample rates.
Note that when the DSP is running, it is forbidden to read or
write either the Code or Data RAMs (except when halted in
STEP mode, see above). Also, after writing to the Code or Data
RAMs to load them, and before starting the DSP, you must reset
the RAM load hardware by writing to the DSPRA register (the
value written is ignored).
IR95 DSP RAM Address Latch (DSPRA) (write only)
Bit 7 - Read
When one, this bit indicates that the next DSP RAM
operation is a read. Zero indicates a write operation.
Bits 5:0 - DSP RAM Address
These bits are the address for the next DSP RAM data
transfer. Note that the Code RAM address can be $00
through $3f, and the Data RAM address can be $00
through $1F.
IR96 Code RAM Data Port (8/16-bit)
Bits B:0 - Code RAM Data
This 8/16-bit port is data to be read from/written to the
DSP Code RAM. The data is the low 12 bits of the word.
IR97 Data RAM Data Port (8/16-bit)
Bits F:0 - Data RAM Data
This 8/16-bit port is the data to be read from/written to
the DSP Data RAM. The data is a full 16-bit word.
Record DMA Control and Status Registers
IR98 Record DMA Control (DMACTL)
Bits 7 - reserved
Bit 6 - TC Reset Mask
When set to 1, this bit masks the ‘DMA Run’ bit reset
upon receipt of TC, terminal count, signal from the ISA
bus. When reset to 0, the ‘DMA Run’ bit will be reset
upon receipt of TC.
Bits 5:1 - reserved
Bit 0 - DMA Run
This bit enables the DMA hardware to begin transfer-
ring data when set to one. It is cleared by either MCR
or receipt of a TC when ‘TC Reset Mask’ is a zero (see
the DMAMODE register for details).
ICS2002
16
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