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參數(shù)資料
| 型號： | ICS2059GI-02T |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK MULT/JITTER ATTEN 16TSSOP |
| 產(chǎn)品變化通告： | Product Discontinuation 13/May/2009 |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 漂移衰減器，多路復(fù)用器 |
| PLL： | 是 |
| 輸入： | 時鐘，晶體 |
| 輸出： | CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 27MHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 2059GI-02T |
ICS2059-02
CLOCK MULTIPLIER AND JITTER ATTENUATOR
VCXO AND SYNTHESIZERS
IDT / ICS CLOCK MULTIPLIER AND JITTER ATTENUATOR
6
ICS2059-02
REV E 051310
Recommended Power Supply Connection for
Optimal Device Performance
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground, shown as CL in the External Component
Schematic. These capacitors are used to adjust the
stray capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
been the crystal and device.
In most cases the load capacitors will not be required.
They should not be stuffed on the prototype evaluation
board as the indiscriminate use of these trim capacitors
will typically cause more crystal centering error than
their absence. If the need for the load capacitors is later
determined, the values will fall within the 1-4 pf range.
The need for, and value of, these trim capacitors can
only be determined at prototype evaluation. Please
refer to MAN05 for the procedure to determine the
component values.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed. Please also refer to the Recommended PCB
Layout drawing on page 7.
1) Each 0.01F decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible. No vias should be used
between decoupling capacitor and VDD pin. The PCB
trace to VDD pin should be kept as short as possible, as
should the PCB trace to the ground via. Distance of the
ferrite bead and bulk decoupling from the device is less
critical.
2) The loop filter components must also be placed close
to the CHGP and VIN pins. CP should be closest to the
device. Coupling of noise from other system signal
traces should be minimized by keeping traces short and
away from active signal traces. Use of vias should be
avoided.
3) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.
4) To minimize EMI, the 33
series termination resistor
(if needed) should be placed close to the clock output.
5) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers (the ferrite bead and bulk decoupling
capacitor can be mounted on the back). Other signal
traces should be routed away from the ICS2059-02.
This includes signal traces just underneath the device,
or on layers adjacent to the ground plane layer used by
the device.
The IDT Applications Note MAN05 may also be
referenced for additional suggestions on layout of the
crystal section.
C onnec tion to 3.3V
Pow er Plane
Ferrite
B ead
B ulk D ec oupling C apac itor
(suc h as 1
F Tantalum )
VD D Pin
0.01
F D ecoupling C apacitors
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