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參數(shù)資料
| 型號(hào)： | ICS252PMLFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 3/10頁 |
| 文件大小： | 0K |
| 描述： | IC CLK SYNTHESIZER FP DUAL 8SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | VersaClock™ |
| 類型： | 時(shí)鐘/頻率合成器，扇出配送，擴(kuò)展頻譜時(shí)鐘發(fā)生器 |
| PLL： | 帶旁路 |
| 輸入： | 時(shí)鐘，晶體 |
| 輸出： | CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 200MHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 252PMLFT |
ICS252
FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER
EPROM CLOCK SYNTHESIZER
IDT FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER 2
ICS252
REV K 030212
Pin Assignment
8-pin (150 mil) SOIC
Output Clock Selection Table
Pin Descriptions
External Components
The ICS252 requires a minimum number of external
components for proper operation.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50
Ω trace (a commonly
used trace impedance), place a 33
Ω resistor in series with
the clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20
Ω.
Decoupling Capacitor
As with any high-performance mixed-signal IC, the ICS252
must be isolated from system power supply noise to perform
optimally.
A decoupling capacitor of 0.01F must be connected
between VDD and the PCB ground plane.
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to ground.
These capacitors are used to adjust the stray capacitance
of the board to match the nominally required crystal load
capacitance. Because load capacitance can only be
increased in this trimming process, it is important to keep
stray capacitance to a minimum by using very short PCB
traces (and no vias) between the crystal and device. Crystal
capacitors must be connected from each of the pins X1 and
X2 to ground.
The value (in pF) of these crystal caps should equal (CL -6
pF)*2. In this equation, CL= crystal load capacitance in pF.
Example: For a crystal with a 16 pF load capacitance, each
crystal capacitor would be 20 pF [(16-6) x 2 = 20].
X 1 /IC L K
VD D
G N D
SEL
CL K 2
CL K 1
X2
1
2
3
4
8
7
6
5
PD T S
SEL
CLK1 (MHz)
CLK2 (MHz)
Spread
Percentage
0
User
Configurable
User
Configurable
User
Configurable
1User
Configurable
User
Configurable
User
Configurable
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
SEL
Input
Select pin for frequency selection on CLK1 and CLK2. Internal pull-up resistor.
2
VDD
Power
Connect to +3.3 V.
3
X1/ICLK
XI
Connect this pin to a crystal or external clock input.
4
X2
XO
Connect this pin to a crystal, or float for clock input.
5
CLK1
Output
Clock1 output. Weak internal pull-down, low when power down.
6
CLK2
Output
Clock2 output. Weak internal pull-down, low when power down.
7
GND
Power
Connect this to ground.
8PDTS
Input
Powers down entire chip. Tri-states CLK outputs when low. No internal pull-up
resistor. The pin must be tied either directly or through the external resistor to
VDD ro GND. External resistor value must be less than 15kOhm.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS252PMT | 功能描述:IC CLK SYNTHESIZER FP DUAL 8SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:VersaClock™ 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時(shí)鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| ICS2572 | 制造商:ICS 制造商全稱:ICS 功能描述:User-Programmable Dual High-Performance Clock Generator |
| ICS2572M | 制造商:ICS 制造商全稱:ICS 功能描述:User-Programmable Dual High-Performance Clock Generator |
| ICS2572M-A01 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| ICS2572M-AXX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
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