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參數(shù)資料
| 型號(hào)： | ICS275PGILFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 5/10頁(yè) |
| 文件大小： | 0K |
| 描述： | VCXO CLK SYNTH TRPL PLL 16-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | VersaClock™ |
| 類型： | 時(shí)鐘/頻率合成器，扇出緩沖器（分配） |
| PLL： | 帶旁路 |
| 輸入： | 晶體 |
| 輸出： | CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:4 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 200MHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 275PGILFT |
ICS275
TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK SYNTHESIZER
EPROM VCXO AND SYNTHESIZER
IDT / ICS TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK SYNTHESIZER 4
ICS275
REV E 081809
errorxtal =actual initial accuracy (in ppm) of the crystal being
measured
If the centering error is less than ±25 ppm, no adjustment is
needed. If the centering error is more than 25ppm negative,
the PC board has excessive stray capacitance and a new
PCB layout should be considered to reduce stray
capacitance. (Alternately, the crystal may be re-specified to
a higher load capacitance. Contact IDT for details.) If the
centering error is more than 25 ppm positive, add identical
fixed centering capacitors from each crystal pin to ground.
The value for each of these caps (in pF) is given by: External
Capacitor = 2 x (centering error)/(trim sensitivity)
Trim sensitivity is a parameter which can be supplied by your
crystal vendor. If you do not know the value, assume it is 30
ppm/pF. After any changes, repeat the measurement to
verify that the remaining error is acceptably low (typically
less than ±25 ppm).
ICS275 Configuration Capabilities
The architecture of the ICS275 allows the user to easily
configure the device to a wide range of output frequencies,
for a given input reference frequency.
The frequency multiplier PLL provides a high degree of
precision. The M/N values (the multiplier/divide values
available to generate the target VCO frequency) can be set
within the range of M = 1 to 1024 and N = 1 to 32,895.
The ICS275 also provides separate output divide values,
from 2 through 63, to allow the two output clock banks to
support widely differing frequency values from the same
PLL.
Each output frequency can be represented as:
IDT VersaClock Software
IDT applies years of PLL optimization experience into a user
friendly software that accepts the user’s target reference
clock and output frequencies and generates the lowest jitter,
lowest power configuration, with only a press of a button.
The user does not need to have prior PLL experience or
determine the optimal VCO frequency to support multiple
output frequencies.
VersaClock software quickly evaluates accessible VCO
frequencies with available output divide values and provides
an easy to understand, bar code rating for the target output
frequencies. The user may evaluate output accuracy,
performance trade-off scenarios in seconds.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS275. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
OutputFreq
REFFreq
M
N
-----
=
Parameter
Condition
Min.
Typ.
Max.
Units
Supply Voltage, VDD
Referenced to GND
7
V
Inputs
Referenced to GND
-0.5
VDD+0.5
V
Clock Outputs
Referenced to GND
-0.5
VDD+0.5
V
Storage Temperature
-65
150
° C
Soldering Temperature
Max 10 seconds
260
° C
Junction Temperature
125
° C
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS275PGIT | 功能描述:VCXO CLK SYNTH TRPL PLL 16-TSSOP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:VersaClock™ 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時(shí)鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| ICS275PGLF | 功能描述:VCXO CLK SYNTH TRPL PLL 16-TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:VersaClock™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| ICS275PGLFT | 功能描述:VCXO CLK SYNTH TRPL PLL 16-TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:VersaClock™ 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| ICS275PGT | 功能描述:VCXO CLK SYNTH TRPL PLL 16-TSSOP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:VersaClock™ 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時(shí)鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| ICS276 | 制造商:ICS 制造商全稱:ICS 功能描述:Triple PLL Field Programmable VCXO Clock Synthesizer |
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