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參數(shù)資料
| 型號： | ICS557GI-03LF |
| 英文描述： | PCI-EXPRESS CLOCK SOURCE |
| 中文描述： | 個PCI - Express時鐘源 |
| 文件頁數(shù)： | 3/9頁 |
| 文件大?。?/td> | 225K |
| 代理商： | ICS557GI-03LF |
PCI-E
XPRESS
C
LOCK
S
OURCE
MDS 557-03 E
3
Revision 061005
Integrated Circuit Systems
●
525 Race Street, San Jose, CA 95126
●
tel (408) 297-1201
●
www.icst.com
ICS557-03
Applications Information
External Components
A minimum number of external components are
required for proper operation.
Decoupling Capacitors
Decoupling capacitors of 0.01
μ
F should be connected
between each VDD pin and the ground plane, as close
to the VDD pin as possible. Do not share ground vias
between components. Route power from power source
through the capacitor pad and then into ICS pin.
Crystal
A 25 MHz fundamental mode parallel resonant crystal
should be used. This crystal must have less than 300
ppm of error across temperature in order for the
ICS557-03 to meet PCI Express specifications.
Crystal Capacitors
Crystal capacitors are connected from pins X1 to
ground and X2 to ground to optimize the accuracy of
the output frequency.
C
L
= Crystal’s load capacitance in pF
Crystal Capacitors (pF) = (C
L
- 8) * 2
For example, for a crystal with a 16 pF load cap, each
external crystal cap would be 16 pF. (16-8)*2=16.
Current Source (Iref) Reference Resistor - R
R
If board target trace impedance (Z) is 50
, then R
R
=
475
(1%), providing IREF of 2.32 mA. The output
current (I
OH
) is equal to 6*IREF.
Output Termination
The PCI-Express differential clock outputs of the
ICS557-03 are open source drivers and require an
external series resistor and a resistor to ground. These
resistor values and their allowable locations are shown
in detail in the
PCI-Express Layout Guidelines
section.
The ICS557-03 can also be configured for LVDS
compatible voltage levels. See the
LVDS Compatible
Layout Guidelines
section.
Output Structures
General PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1. Each 0.01μF decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible.
2. No vias should be used between decoupling
capacitor and VDD pin.
3. The PCB trace to VDD pin should be kept as short
as possible, as should the PCB trace to the ground via.
Distance of the ferrite bead and bulk decoupling from
the device is less critical.
4. An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers (any ferrite beads and bulk decoupling
capacitors can be mounted on the back). Other signal
traces should be routed away from the ICS557-03.This
includes signal traces just underneath the device, or on
layers adjacent to the ground plane layer used by the
device.
R
R
475
6*IREF
=2.3 mA
IREF
See Output Termination
Sections - Pages 3 ~ 5
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS557GI-03LFT | PCI-EXPRESS CLOCK SOURCE |
| ICS557GI-03T | PCI-EXPRESS CLOCK SOURCE |
| ICS570A | Multiplier and Zero Delay Buffer |
| ICS570AI | Multiplier and Zero Delay Buffer |
| ICS570AIT | Multiplier and Zero Delay Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS557GI-03LFT | 功能描述:IC CLK SOURCE PCI EXPRSS 16TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:PCI Express® (PCIe) 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| ICS557GI-03T | 功能描述:IC CLK SOURCE PCI EXPRSS 16TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:PCI Express® (PCIe) 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| ICS557GI-05A | 制造商:ICS 制造商全稱:ICS 功能描述:Quad Differential PCI-Express Clock Source |
| ICS557GI-05ALF | 功能描述:IC CLK SOURCE QUAD PCI 20-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:PCI Express® (PCIe) 標(biāo)準(zhǔn)包裝:1 系列:- 類型:時鐘/頻率發(fā)生器，多路復(fù)用器 PLL:是 主要目的:存儲器，RDRAM 輸入:晶體 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱:296-6719-6 |
| ICS557GI-05ALFT | 功能描述:IC CLK SOURCE QUAD DIFF 20TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:PCI Express® (PCIe) 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
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