參數(shù)資料
型號(hào): ICS557GI-05ALF
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 8/12頁(yè)
文件大?。?/td> 0K
描述: IC CLK SOURCE QUAD PCI 20-TSSOP
產(chǎn)品培訓(xùn)模塊: PCI-Express
特色產(chǎn)品: PCI-Express Clock Source
標(biāo)準(zhǔn)包裝: 74
系列: PCI Express® (PCIe)
類型: 擴(kuò)展頻譜時(shí)鐘發(fā)生器,扇出緩沖器(分配)
PLL:
主要目的: PCI Express(PCIe)
輸入: 時(shí)鐘,晶體
輸出: HCSL,LVDS
電路數(shù): 1
比率 - 輸入:輸出: 1:4
差分 - 輸入:輸出: 無/是
頻率 - 最大: 200MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 管件
產(chǎn)品目錄頁(yè)面: 1252 (CN2011-ZH PDF)
其它名稱: 557GI-05ALF
800-1067
800-1067-5
800-1067-ND
ICS557-05A
QUAD DIFFERENTIAL PCI-EXPRESS GEN1 CLOCK SOURCE
PCIE SSCG
IDT
QUAD DIFFERENTIAL PCI-EXPRESS GEN1 CLOCK SOURCE
5
ICS557-05A
REV O 112111
Output Structures
General PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1. Each 0.01F decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible.
2. No vias should be used between decoupling capacitor
and VDD pin.
3. The PCB trace to VDD pin should be kept as short as
possible, as should the PCB trace to the ground via.
Distance of the ferrite bead and bulk decoupling from the
device is less critical.
4. An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (any ferrite beads and bulk decoupling capacitors can
be mounted on the back). Other signal traces should be
routed away from the ICS557-05A.This includes signal
traces just underneath the device, or on layers adjacent to
the ground plane layer used by the device.
R
R 475
6*IREF
=2.3 mA
IREF
See Output Termination
Sections - Pages 3 ~ 5
Ω
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ICS557GI-05ALFTR 制造商:ICS 制造商全稱:ICS 功能描述:Quad Differential PCI-Express Clock Source
ICS557GI-05AT 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:QUAD DIFFERENTIAL PCI-EXPRESS CLOCK SOURCE
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