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參數(shù)資料
| 型號： | ICS571MT |
| 廠商： | INTEGRATED CIRCUIT TECHNOLOGY CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 571 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 封裝： | SOIC-8 |
| 文件頁數(shù)： | 1/4頁 |
| 文件大?。?/td> | 1926K |
| 代理商： | ICS571MT |
ICS571
Low Phase Noise Zero Delay Buffer
MDS 571 F
1
Revision 062006
Printed 06/20/06
Integrated Circuit Systems, Inc.525 Race StreetSan JoseCA95126(408)297-1201tel(408)295-9818fax
Packaged in 8 pin SOIC (Pb free available)
Can function as low phase noise x2 multiplier.
Low skew outputs. One is ÷2 of other.
Input clock frequency up to 160 MHz at 3.3V.
Phase noise of better than -100 dBc/Hz from
1kHz to 1MHz offset from carrier
Can recover poor input clock duty cycle.
Output clock duty cycle of 45/55 at 3.3V.
High drive strength for >100 MHz outputs.
Full CMOS clock swings with 25mA drive
capability at TTL levels.
Advanced, low power CMOS process.
Operating voltages of 3.0 to 5.5 V.
The ICS571 is a high speed, high output drive, low
phase noise Zero Delay Buffer (ZDB) which
integrates ICS’ proprietary analog/digital Phase
Locked Loop (PLL) techniques. ICS introduced
the world standard for these devices in 1992 with
the debut of the AV9170, and updated that with
the ICS570. The ICS571, part of ICS’
ClockBlocks family, was designed to operate at
higher frequencies, with faster rise and fall times,
and with lower phase noise. The zero delay feature
means that the rising edge of the input clock aligns
with the rising edges of both outputs, giving the
appearance of no delay through the device. There
are two outputs on the chip, one being a low-skew
divide by two of the other.
The chip is ideal for synchronizing outputs in a
large variety of systems, from personal computers
to data communications to video. By allowing off-
chip feedback paths, the ICS571 can eliminate the
delay through other devices. The use of dividers in
the feedback path will enable the part to multiply
by more than two.
Block Diagram
Description
Features
Phase
Detector,
Charge
Pump, and
Loop Filter
Voltage
Controlled
Oscillator
CLK
Output
Buffer
ICLK
CLK/2
Output
Buffer
FBIN
÷2
External feedback can come from CLK or CLK/2 (see table on page 2).
相關PDF資料 |
PDF描述 |
|---|---|
| ICS571MLF | 571 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| ICS571M | 571 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| ICS574MILF | 574 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| ICS574MLFT | 574 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| ICS574M | 574 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ICS574 | 制造商:ICS 制造商全稱:ICS 功能描述:Zero Delay, Low Skew Buffer |
| ICS574M | 功能描述:IC CLOCK ZDB 1:4 160MHZ 8SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 產品變化通告:Product Discontinuation 04/May/2011 標準包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| ICS574MI | 功能描述:IC CLOCK ZDB 1:4 160MHZ 8SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 產品變化通告:Product Discontinuation 04/May/2011 標準包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| ICS574MILF | 功能描述:IC CLOCK ZDB 1:4 160MHZ 8SOIC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應商設備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| ICS574MILFT | 功能描述:IC CLOCK ZDB 1:4 160MHZ 8SOIC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應商設備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
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