參數(shù)資料
型號(hào): ICS581G-02LFT
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 7/10頁
文件大?。?/td> 0K
描述: IC CLK MUX GLITCH FREE 16-TSSOP
產(chǎn)品培訓(xùn)模塊: Clock Distibution and Generation 1.0
標(biāo)準(zhǔn)包裝: 2,500
系列: ClockBlocks™
類型: 扇出緩沖器(分配),零延遲緩沖
PLL:
輸入: 時(shí)鐘
輸出: 時(shí)鐘
電路數(shù): 1
比率 - 輸入:輸出: 2:4
差分 - 輸入:輸出: 無/無
頻率 - 最大: 200MHz
除法器/乘法器: 是/無
電源電壓: 3 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 帶卷 (TR)
其它名稱: 581G-02LFT
ICS581-01/02
ZERO DELAY GLITCH-FREE CLOCK MULTIPLEXER
ZDB AND MULTIPLEXER
IDT / ICS ZERO DELAY GLITCH-FREE CLOCK MULTIPLEXER
6
ICS581-01/02
REV L 051310
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85
° C
Note 1: Assumes clocks with same rise times, measured at VDD/2.
Note 2: Assumes identically loaded outputs with identical rise times, measured at VDD/2. The maximum skew between any two
clocks is 250 ps not 500 ps.
Note 3: Time taken for output to lock to new clock when mux selection changed from INA to INB.
Note 4. With 50 MHz on INA and 150 MHz on INB.
Note 5: With 100 MHz on both INA and INB, 180
° out of phase.
Input Capacitance
CIN
5pF
Output High Voltage
VOH
IOH = -12 mA
VDD-0.5
V
Output Low Voltage
VOL
IOL = 12 mA
0.5
V
Short Circuit Current
IOS
±70
mA
On-chip Pull-up
Resistor
RPU
S1=0, OE1=0,
SELA, DIV pins
250
k
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Input Frequency
fIN
6200
MHz
Input Clock Duty Cycle
at VDD/2
30
70
%
Skew
tSKEW
selected input clock to
FBIN, Note 1
-250
0
250
ps
between any output
clocks, Note 2
-250
0
250
ps
Transition Detector
Timeout
ICS581-02 only
DIV = 0
2
3
4
INB
periods
DIV = 1
32
48
64
INB
periods
Frequency Transition Time
tTRAN
50 to 150 MHz, Note 3, 4
70
200
s
100 to 100 MHz, Note 3,
5
410
s
Output Clock Rise Time
tOR
0.8 V to 2.0 V
1
2
ns
Output Clock Fall Time
tOF
2.0 V to 0.8 V
1
2
ns
Output Clock Duty Cycle
less than 133 MHz
at VDD/2, no load
45
55
%
greater than 133 MHz
at VDD/2, no load
40
60
%
with S0=S1=1
at VDD/2, no load
40
60
%
Absolute Output Clock
Period Jitter
tJA
Deviation from mean
±150
ps
One Sigma Output Clock
Period Jitter
tJA
40
ps
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
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