參數(shù)資料
型號(hào): ICS601R-25LFT
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 1/6頁(yè)
文件大?。?/td> 0K
描述: IC CLOCK MULTIPLIER 1:5 20-SSOP
標(biāo)準(zhǔn)包裝: 2,500
類型: 時(shí)鐘/頻率合成器
PLL:
輸入: 時(shí)鐘,晶體
輸出: CMOS
電路數(shù): 1
比率 - 輸入:輸出: 1:5
差分 - 輸入:輸出: 無(wú)/無(wú)
頻率 - 最大: 156MHz
除法器/乘法器: 是/是
電源電壓: 2.97 V ~ 3.63 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 20-SSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 20-QSOP
包裝: 帶卷 (TR)
其它名稱: 601R-25LFT
DATASHEET
LOW PHASE NOISE 1 TO 5 CLOCK MULTIPLIER
ICS601-25
IDT / ICS LOW PHASE NOISE 1 TO 5 CLOCK MULTIPLIER
1
ICS601-25
REV E 051310
Description
The ICS601-25 is a low-cost, low phase noise, high
performance clock synthesizer for applications which
require low phase noise, low jitter, and low skew fanout. It is
IDT’s lowest phase noise multiplier, and also the lowest
CMOS part in the industry. Using IDT’s patented analong
and digital Phase Locked Loop (PLL) techniques, the chip
accepts a 10-27 MHz crystal or clock input, and produces
output clocks up to 156 MHz.
Features
Packaged in 20-pin SSOP
Uses fundamental 10 - 27 MHz crystal or clock
Output clocks up to 156 MHz
Low phase noise: -132 dBc/Hz at 10 kHz
Five low skew (<250 ps) outputs
Low jitter - 18 ps one sigma at 125 MHz
Full swing CMOS outputs with 25 mA drive capability at
TTL levels
Powerdown mode lowers power consumption
Advanced, low power, sub-micron CMOS process
Industrial temperature version available
Pb (lead) free package
Operating voltage of 3.3 V
Block Diagram
CLK1
ROM Based
Multipliers
VCO
Divide
X1/ICLK
X2
Crystal or
clock input
Crystal
Oscillator
Reference
Divider
Phase
Comparator
VDD
Charge
Pump
Loop
Filter
VCO
S3:0
PD
CLK5
CLK4
CLK3
CLK2
5
GND
3
4
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