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參數(shù)資料
| 型號： | ICS650-07C |
| 英文描述： | Networking Clock Source |
| 中文描述： | 網(wǎng)絡(luò)時(shí)鐘源 |
| 文件頁數(shù)： | 4/5頁 |
| 文件大小： | 73K |
| 代理商： | ICS650-07C |
ICS650-07C
Networking Clock Source
MDS 650-07C A
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126(408)295-9800tel www.icst.com
4
Revision 101399
Printed 11/28/00
PRELIMINARY INFORMATION
Parameter
ABSOLUTE MAXIMUM RATINGS (note 1)
Supply voltage, VDD
Inputs and Clock Outputs
Ambient Operating Temperature
Ambient Operating Temperature, I version
Soldering Temperature
Storage temperature
DC CHARACTERISTICS (VDD = 5.0V unless noted)
Operating Voltage, VDD
Input High Voltage, VIH, X1 pin only
Input Low Voltage, VIL, X1 pin only
Input High Voltage, VIH, all TI type inputs
Input Low Voltage, VIL, all TI type inputs
Input High Voltage, VIH, all I type inputs
Input Low Voltage, VIL, all I type inputs
Output High Voltage, VOH
Output Low Voltage, VOL
Output High Voltage, VOH, CMOS level
Operating Supply Current, IDD
Short Circuit Current
Internal pull-up resistor
AC CHARACTERISTICS (VDD = 5.0V unless noted)
Input Frequency
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
Frequency error
Absolute Jitter, short term
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
Conditions
Minimum
Typical
Maximum
Units
Referenced to GND
Referenced to GND
7
V
V
°C
°C
°C
°C
-0.5
0
-40
VDD+0.5
70
85
260
150
Industrial temp
Max of 20 seconds
-65
3
5.5
V
V
V
V
V
V
V
V
V
V
Clock input
Clock input
VDD/2 + 1
VDD/2
VDD/2
VDD/2 - 1
VDD-0.5
0.5
2
0.8
IOH=-25mA
IOL=25mA
IOH=-8mA
No Load
Each output
ACS1, BCS1, OE
2.4
0.4
VDD-0.4
60
±100
200
mA
mA
k
10
12.5 or 25
27
1.5
1.5
60
0
MHz
ns
ns
%
ppm
ps
0.8 to 2.0V
2.0 to 0.8V
At VDD/2
All clocks
Variation from mean
40
50
150
Electrical Specifications
External Components
The ICS650-07C requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.01μF should be connected between each VDD and GND (pins 4 and 6, pins 16 and 14), as
close to the ICS650-07 as possible. A series termination resistor of 33
may be used for each clock output.
The crystal must be connected as close to the chip as possible. The crystal should be a fundamental mode
(do not use third overtone), parallel resonant. Crystal capacitors should be connected from pins X1 to
ground and X2 to ground to optimize the initial accuracy. The value of these capacitors is given by the
following equation, where C
L
is the crystal load capacitance: Crystal caps (pF) = (C
L
-6) x 2. So for a crystal
with 16 pF load capacitance, two 20 pF caps should be used.
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