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參數(shù)資料
| 型號(hào)： | ICS660GIT |
| 英文描述： | Digital Video Clock Source |
| 中文描述： | 數(shù)字視頻時(shí)鐘源 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 127K |
| 代理商： | ICS660GIT |
Digital Video Clock Source
MDS 660 E
3
Revision 040104
Integrated Circuit Systems, Inc.
●
525 Race Street, San Jose, CA 95126
●
tel (408) 297-1201
●
www.icst.com
ICS660
Application Information
Series Termination Resistor
Clock output traces should use series termination. To
series terminate a 50
trace (a commonly used trace
impedance), place a 33
resistor in series with the
clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20
.
Decoupling Capacitors
As with any high-performance mixed-signal IC, the
ICS660 must be isolated from system power supply
noise to perform optimally.
Decoupling capacitors of 0.01μF must be connected
between each VDD and the PCB ground plane. To
further guard against interfering system supply noise,
the ICS660 should use one common connection to the
PCB power plane as shown in the diagram on the next
page. The ferrite bead and bulk capacitor help reduce
lower frequency noise in the supply that can lead to
output clock phase modulation.
Recommended Power Supply Connection for
Optimal Device Performance
All power supply pins must be connected to the same
voltage, except VDDR and VDDO, which may be
connected to a lower voltage in order to change the
output level. If the reference output is not used, ground
VDDR.
Crystal Load Capacitors
If a crystal is used, the device crystal connections
should include pads for capacitors from X1 to ground
and from X2 to ground. These capacitors are used to
adjust the stray capacitance of the board to match the
nominally required crystal load capacitance. To reduce
possible noise pickup, use very short PCB traces (and
no vias) been the crystal and device.
The value of the load capacitors can be roughly
determined by the formula C = 2(C
L
- 6) where C is the
load capacitor connected to X1 and X2, and C
L
is the
specified value of the load capacitance for the crystal.
A typical crystal C
L
is 18 pF, so C = 2(18 - 6) = 24 pF.
Because these capacitors adjust the stray capacitance
of the PCB, check the output frequency using your final
layout to see if the value of C should be changed.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) Each 0.01μF decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible. No vias should be used
between decoupling capacitor and VDD pin. The PCB
trace to VDD pin should be kept as short as possible,
as should the PCB trace to the ground via. Distance of
the ferrite bead and bulk decoupling from the device is
less critical.
2) The external crystal should be mounted next to the
device with short traces. The X1 and X2 traces should
not be routed next to each other with minimum spaces,
instead they should be separated and away from other
traces.
3) To minimize EMI, and obtain the best signal integrity,
the 33
series termination resistor should be placed
close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers (the ferrite bead and bulk decoupling
capacitor can be mounted on the back). Other signal
traces should be routed away from the ICS660. This
includes signal traces just underneath the device, or on
layers adjacent to the ground plane layer used by the
device.
Connection to 3.3V
Power Plane
Ferrite
Bead
Bulk Decoupling Capacitor
(such as 1
F Tantalum)
VDD Pin
VDD Pin
VDD Pin
0.01
F Decoupling Capacitors
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS660GITR | 制造商:ICS 制造商全稱:ICS 功能描述:Digital Video Clock Source |
| ICS661 | 制造商:ICS 制造商全稱:ICS 功能描述:Precision Audio Clock Source |
| ICS66-1 | 制造商:Thomas & Betts 功能描述:INSULATED SERV.ENTR.SLEEVE 制造商:Thomas & Betts 功能描述:Cable Accessories Compression Splice Aluminum |
| ICS661GI | 功能描述:IC CLK SOURCE PREC AUD 16-TSSOP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時(shí)鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| ICS661GILF | 功能描述:IC AUDIO CLK SOURCE PREC 16TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
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