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參數(shù)資料
| 型號(hào)： | ICS663MLFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL BUILDING BLOCK 8-SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 鎖相環(huán)路（PLL） |
| PLL： | 是 |
| 輸入： | CMOS |
| 輸出： | CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 120MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.13 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 663MLFT |
ICS663
PLL BUILDING BLOCK
IDT / ICS PLL BUILDING BLOCK
6
ICS663
REV E 012006
Determining the Loop Filter Values
The loop filter components consist of C1, C2, and RZ.
Calculating these values is best illustrated by an example.
Using the example in Figure 1, we can synthesize 20 MHz
from a 200 kHz input.
The phase locked loop may be approximately described by
the following equations:
Bandwidth
Damping factor,
where:
KO = VCO gain (MHz/Volt)
Icp = Charge pump current (A)
N = Total feedback divide from VCO,
including the internal VCO post divider
C1 = Loop filter capacitor (Farads)
RZ = Loop filter resistor (Ohms)
As a general rule, the bandwidth should be at least 20 times
less than the reference frequency, i.e.,
In this example, using the above equation, bandwidth
should be less than or equal to 10 kHz. By setting the
bandwith to 10kHz and using the first equation, RZ can be
determined since all other variables are known. In the
example of Figure 1, N = 200, comprising the divide by 2 on
the chip (VCO post divider) and the external divide by 100.
Therefore, the bandwidth equation becomes:
and RZ = 25 k
Choosing a damping factor of 0.7 (a minimal damping factor
than can be used to ensure fast lock time), damping factor
equation becomes:
and C1 = 1.25 nF (1.2 nF is the nearest standard value).
The capacitor C2 is used to damp transients from the
charge pump and should be approximately 1/20th the size
of C1, i.e.,
Therefore, C2 = 60 pF (56 pF nearest standard value).
To summarize, the loop filter components are:
C1 = 1.2 nf
C2 = 56 pf
Rz = 25 k
RZ KO ICP
(
)
2
π N
------------------------------------------
=
ζ
RZ
2
------
KO ICP C1
N
------------------------------------
=
BW REFIN
() 20
≤
0,000
RZ 200 2.5
2
π 200
--------------------------------------
=
.7
25 000
,
2
-------------------
200
2.5
C
200
------------------------------------
=
C2 C1 20
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| ICS663MT | 功能描述:IC PLL BUILDING BLOCK 8-SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時(shí)鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
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| ICS664-02 | 制造商:ICS 制造商全稱:ICS 功能描述:PECL Digital Video Clock Source |
| ICS664-03 | 制造商:ICS 制造商全稱:ICS 功能描述:Digital Video Clock Source |
| ICS664-03LF | 制造商:ICS 制造商全稱:ICS 功能描述:Digital Video Clock Source |
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