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參數(shù)資料
| 型號： | ICS810001BK-21T |
| 英文描述： | FEMTOCLOCKS-TM DUAL VCXO VIDEO PLL |
| 中文描述： | FEMTOCLOCKS -商標(biāo)雙壓控視頻鎖相環(huán) |
| 文件頁數(shù)： | 14/21頁 |
| 文件大小： | 244K |
| 代理商： | ICS810001BK-21T |
810001BK-21
www.icst.com/products/hiperclocks.html
REV. A AUGUST 12, 2005
14
Integrated
Circuit
Systems, Inc.
ICS810001-21
F
EMTO
C
LOCKS
D
UAL
VCXO V
IDEO
PLL
PRELIMINARY
D
ESCRIPTION
OF
THE
PLL S
TAGES
The ICS843002-21 is a two stage device, a VCXO PLL fol-
lowed by a low phase noise FemtoClock frequency multiplier.
The VCXO uses an external pullable crystal which can be
pulled ±100ppm by the VCXO PLL circuitry to phase lock it to
the input reference frequency. There are two VCXO crystal
ports in order to provide VCXO frequency versatility. For HDTV
applications, this allows the use of a 26.973027MHz crystal
for the generation of 74.175MHz, or a 27.00MHz crystal for
the generation of 74.25MHz, for example.
The VCXO output frequency can be output directly from the
device, or it can be passed to the FemtoClock frequency
multiplier which will multiply it up to a higher frequency.
VCXO PLL L
OOP
R
ESPONSE
C
ONSIDERATIONS
Loop response characteristics of the VCXO PLL is affected
by the VCXO feedback divider value (bandwidth and damping
factor), and by the external loop filter components (bandwidth,
damping factor, and 2
nd
frequency response). A practical range
of VCXO PLL bandwidth is from about 1Hz to about 1kHz.
The setting of VCXO PLL bandwidth and damping factor is
covered later in this document. A PC based PLL bandwidth
calculator is also under development. For assistance with loop
bandwidth suggestions or value calculation, please contact
ICS applications.
Table 3A shows frequency translation configuration examples.
Note that in the first two V3:V0 selections the VCXO PLL feed-
back divider is the same value of 1000. This means the VCXO
PLL loop response (bandwidth and damping factor) will be the
same for all of these settings.
The same is true for V3:V0 = 0010 through 0110. This means
the device can be configured to translate between 74.175MHz,
74.25MHz, and 27MHz (from any one to another, all nine com-
binations) and it will maintain the same loop response char-
acteristics. This is also true for V3:V0 = 1000 through 1010.
For high VCXO PLL feedback divider values, the phase de-
tector rate, and therefore loop filter charge pulse rate, is greatly
reduced. To prevent output clock wander, low leakage capaci-
tors should be used. In addition, when loop bandwidth is low
(say below 20Hz), capacitors with low microphonic sensitiv-
ity should be used. PPS film type capacitors are one type that
perform well in this environment. Below 5Hz, shielding should
be considered to prevent excessive phase wander (low fre-
quency phase jitter or clock phase deviation).
S
ETTING
THE
VCXO PLL L
OOP
R
ESPONSE
The VCXO PLL loop response is determined both by fixed device
characteristics and by other characterizes set by the user. This
includes the values of R
, C
, C
and R
as shown in the
External VCXO PLL Components figure on this page.
The VCXO PLL loop bandwidth is approximated by:
W
HERE
:
R
S
= Value of resistor R
S
in loop filter in Ohms
I
CP
= Charge pump current in amps (see table on page 12)
K
= VCXO Gain in Hz/V
Feedback Divider = 1 to 11011 (as determined by inputs
V3:V0)
The above equation calculates the “normalized” loop bandwidth
(denoted as “NBW”) which is approximately equal to the - 3dB
bandwidth. NBW does not take into account the effects of
damping factor or the second pole imposed by C
. It does,
however, provide a useful approximation of filter performance.
To prevent jitter on the clock output due to modulation of the
VCXO PLL by the phase detector frequency, the following general
rule should be observed:
(Phase Detector) = Input Frequency ÷ Pre-Divider)
The PLL loop damping factor is determined by:
W
HERE
:
C
S
= Value of capacitor C
S
in loop filter in Farads
NBW (VCXO PLL) =
R
S
x I
CP
x K
O
2
π
x Feedback Divider
NBW (VCXO PLL)
≤
(Phase Detector)
20
DF = x
R
S
2
I
CP
x C
S
x K
O
Feedback Divider
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| ICS810001BK-22LF | 功能描述:IC CLK SYNC DL VCXO PLL 32 VFQFN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:HiPerClockS™, FemtoClock™ 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| ICS810001BK-22LFT | 功能描述:IC CLK SYNC DL VCXO PLL 32 VFQFN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:HiPerClockS™, FemtoClock™ 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| ICS810001DK-21LF | 功能描述:IC CLK GEN SYNC VCXO DL 32VFQFN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:HiPerClockS™, FemtoClock™ 標(biāo)準(zhǔn)包裝:1 系列:- 類型:時鐘/頻率發(fā)生器，多路復(fù)用器 PLL:是 主要目的:存儲器，RDRAM 輸入:晶體 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱:296-6719-6 |
| ICS810001DK-21LFT | 功能描述:IC CLK GEN SYNC VCXO DL 32VFQFN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:HiPerClockS™, FemtoClock™ 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| ICS810-06 | 制造商:ICS 制造商全稱:ICS 功能描述:VCXO-TO-6 LVCMOS OUTPUTS |
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