參數(shù)資料
型號(hào): ICS81006AK
英文描述: VCXO-TO-6 LVCMOS OUTPUTS
中文描述: 壓控到6 LVCMOS輸出
文件頁(yè)數(shù): 10/14頁(yè)
文件大?。?/td> 165K
代理商: ICS81006AK
81006AK
www.icst.com/products/hiperclocks.html
REV. A JANUARY 4, 2006
10
Integrated
Circuit
Systems, Inc.
ICS81006
VCXO-
TO
-6 LVCMOS O
UTPUTS
l
b
m
y
S
C
C
r
e
m
a
V
a
V
a
r
w
a
o
g
P
L
H
s
n
o
n
V
0
=
3
=
o
C
V
C
V
C
t
e
T
m
u
m
i
M
l
c
y
T
4
1
6
2
m
u
m
i
a
M
s
U
F
p
F
p
W
O
L
_
V
e
e
c
c
n
n
a
a
a
a
p
p
a
a
C
C
r
r
H
G
I
H
_
V
h
V
T
ABLE
6. V
ARACTOR
P
ARAMETERS
F
ORMULAS
(
C
) (
) (
+
)
(
)
Low
V
S
L
Low
V
S
L
Low
V
S
L
Low
V
S
L
Low
C
C
C
C
C
C
C
C
C
C
C
C
_
2
2
_
1
1
_
2
2
_
1
1
+
+
+
+
+
+
+
+
=
(
C
) (
) (
+
)
(
)
High
V
S
L
High
V
S
L
High
V
S
L
High
V
S
L
High
C
C
C
C
C
C
C
C
C
C
C
C
_
2
2
_
1
1
_
2
2
_
1
1
+
+
+
+
+
+
+
+
=
6
0
1
0
0
1
0
10
1
2
1
1
2
1
)
(
+
+
=
C
C
C
C
C
C
C
C
TPR
Range
Pull
Total
High
Low
C
Low
is the effective capacitance due to the low varactor capacitance, load capacitance and stray capacitance.
C
Low
determines the high frequency component on the TPR.
C
High
is the effective capacitance due to the high varactor capacitance, load capacitance and stray capacitance.
C
High
determines the low frequency component on the TPR.
Absolute Pull Range (APR) = Total Pull Range – (Frequency Tolerance + Frequency Stability + Aging)
E
XAMPLE
C
ALCULATIONS
Using the tables and figures above, we can now calculate the
TPR and APR of the VCXO using the example crystal
parameters. For the numerical example below there were some
assumptions made. First, the stray capacitance (C
, C
), which
is all the excess capacitance due to board parasitic, is 4pF.
Second, the expected lifetime of the project is 5 years; hence
(
(
pf
pf
4
15
4
0
+
+
+
the inaccuracy due to aging is ±15ppm. Third, though many
boards will not require load tuning capacitors (C
, C
), it is
recommended for long-term consistent performance of the
system that two tuning capacitor pads be placed into every
design. Typical values for the load tuning capacitors will range
from 0 to 4pF.
(
(
pf
pf
0
6
29
4
0
+
+
+
) (
) (
)
)
pf
pf
pf
pf
pf
pf
pf
C
Low
7
4
15
4
0
4
15
+
4
0
4
15
4
0
=
+
+
+
+
+
=
) (
) (
)
)
pf
pf
pf
pf
pf
pf
pf
C
High
8
16
6
29
4
6
29
4
0
6
29
4
0
=
+
+
+
+
+
+
=
ppm
pF
pF
pF
pF
TPR
5
226
10
4
8
16
1
220
2
1
4
7
1
220
2
1
6
=
+
+
=
TPR = ±113.25ppm
APR = 113.25ppm – (20ppm + 20ppm + 15ppm) = ±58.25ppm
The example above will ensure a total pull range of
±113.25 ppm with an APR of ±58.25ppm. Many times, board
designers may select their own crystal based on their
application. If the application requires a tighter APR, a crystal
with better pullability (C0/C1 ratio) can be used. Also, with the
equations above, one can vary the frequency tolerance,
temperature stability, and aging or shunt capacitance to achieve
the required pullability.
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