IDT / ICS VCXO-TO-LVCMOS/LVTTL OUTPUT
參數(shù)資料
型號(hào): ICS810525AGILFT
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 11/12頁
文件大?。?/td> 0K
描述: IC VCXO-LVCMOS/LVTTL 16-TSSOP
標(biāo)準(zhǔn)包裝: 2,500
系列: HiPerClockS™, FemtoClock™
類型: 壓控晶體振蕩器(VCXO)
PLL:
輸入: LVCMOS,LVTTL
輸出: LVCMOS,LVTTL
電路數(shù): 1
比率 - 輸入:輸出: 2:1
差分 - 輸入:輸出: 無/無
頻率 - 最大: 25MHz
除法器/乘法器: 無/是
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 帶卷 (TR)
其它名稱: 810525AGILFT
IDT / ICS VCXO-TO-LVCMOS/LVTTL OUTPUT
8
ICS810525AGI REV. B FEBRUARY 24, 2009
ICS810525I
VCXO-TO-LVCMOS/LVTTL OUTPUT
VCXO-PLL EXTERNAL COMPONENTS
Choosing the correct external components and having a proper
printed circuit board (PCB) layout is a key task for quality
operation of the VCXO-PLL. In choosing a crystal, special
precaution must be taken with the package and load
capacitance (C
L
). In addition, frequency, accuracy and
temperature range must also be considered. Since the pulling
range of a cr ystal also va r ies with the package, it is
recommended that a metal-canned package like HC49 be used.
Generally, a metal-canned package has a larger pulling range
than a surface mounted device (SMD). For crystal selection
information, refer to the
VCXO Crystal Selection Application
Note.
The crystal’s load capacitance C
L
characteristic determines its
resonating frequency and is closely related to the VCXO tuning
range. The total external capacitance seen by the crystal when
installed on a board is the sum of the stray board capacitance,
IC package lead capacitance, internal varactor capacitance and
any installed tuning capacitors (C
TUNE
).
If the crystal’s C
L
is greater than the total external capacitance,
the VCXO will oscillate at a higher frequency than the crystal
specification. If the crystal’s C
L
is lower than the total external
capacitance, the VCXO will oscillate at a lower frequency than
VCXO-PLL APPROXIMATE LOOP BANDWIDTH SELECTION TABLE
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VCXO CHARACTERISTICS TABLE
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the crystal specification. In either case, the absolute tuning
range is reduced. The correct value of C
L
is dependent on the
characteristics of the VCXO. The recommended C
L
in the Crystal
Parameter Table balances the tuning range by centering the
tuning curve.
The
VCXO-PLL Loop Bandwidth Selection Table shows R
S
, C
S
and C
P
values for recommended high, mid and low loop
bandwidth configurations. The device has been characterized
using these parameters. For other configurations, refer to the
Loop Filter Component Selection for VCXO Based PLLs
Application Note.
The crystal and external loop
filter components should be
kept as close as possible to the
device. Loop filter and crystal
traces should be kept short and
separated from each other.
Other signal traces should be
kept separate and not r un
underneath the device, loop
filter or crystal components.
LF0
LF1
XTAL_IN
XTAL_OUT
RS
C
S
C
P
C
TUNE
C
TUNE
25MHz
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