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參數(shù)資料
| 型號： | ICS813001AGILFT |
| 英文描述： | DUAL VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK-TM PLL |
| 中文描述： | 雙壓控W/3.3V，2.5伏的LVPECL FEMTOCLOCK，商標(biāo)鎖相環(huán) |
| 文件頁數(shù)： | 12/18頁 |
| 文件大?。?/td> | 237K |
| 代理商： | ICS813001AGILFT |
813001AGI
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 2, 2005
12
Integrated
Circuit
Systems, Inc.
ICS813001I
D
UAL
VCXO
W
/3.3V, 2.5V LVPECL
F
EMTO
C
LOCK
PLL
T
ERMINATION
FOR
3.3V LVPECL O
UTPUT
The clock layout topology shown below is a typical ter-
mination for LVPECL outputs. The two different layouts
mentioned are recommended only as guidelines.
V
CC
- 2V
50
Ω
50
Ω
RTT
Z
o
= 50
Ω
Z
o
= 50
Ω
FOUT
FIN
RTT =
Z
o
1
((V
OH
+ V
OL
) / (V
CC
– 2)) – 2
3.3V
125
Ω
125
Ω
84
Ω
84
Ω
Z
o
= 50
Ω
Z
o
= 50
Ω
FOUT
FIN
FOUT and nFOUT are low impedance follower outputs
that generate ECL/LVPECL compatible outputs. There-
fore, terminating resistors (DC current path to ground)
or current sources must be used for functionality. These
outputs are designed to drive 50
Ω
transmission lines.
F
IGURE
5B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
5A. LVPECL O
UTPUT
T
ERMINATION
Matched impedance techniques should be used to maxi-
mize operating frequency and minimize signal distor-
tion.
Figures 5A and 5B
show two different layouts which
are recommended only as guidelines. Other suitable
clock layouts may exist and it would be recommended
that the board designers simulate to guarantee compat-
ibility across all printed circuit and clock component pro-
cess variations.
I
NPUTS
:
C
RYSTAL
I
NPUT
:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating.
Though not required, but for additional protection, a 1k
Ω
resistor can be tied from XTAL_IN to ground.
CLK I
NPUT
:
For applications not requiring the use of a clock input, it can
be left floating. Though not required, but for additional
protection, a 1k
Ω
resistor can be tied from the CLK input to
ground.
CLK/nCLK I
NPUT
:
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required,
but for additional protection, a 1k
Ω
resistor can be tied from
CLK to ground.
LVCMOS C
ONTROL
P
INS
:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
Ω
resistor can be used.
VC input pin - do not float, must be biased.
R
ECOMMENDATIONS
FOR
U
NUSED
I
NPUT
AND
O
UTPUT
P
INS
O
UTPUTS
:
LVPECL O
UTPUT
All unused LVPECL outputs can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or
terminated.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS813001AGIT | 制造商:ICS 制造商全稱:ICS 功能描述:DUAL VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK-TM PLL |
| ICS813001I | 制造商:ICS 制造商全稱:ICS 功能描述:DUAL VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK-TM PLL |
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