參數(shù)資料
型號: ICS830154AMI-08LF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 12/16頁
文件大小: 0K
描述: IC CLOCK BUFFER 1:4 160MHZ 8SOIC
標準包裝: 194
系列: HiPerClockS™
類型: 扇出緩沖器(分配)
電路數(shù): 1
比率 - 輸入:輸出: 1:4
差分 - 輸入:輸出: 無/無
輸入: LVCMOS
輸出: LVCMOS
頻率 - 最大: 160MHz
電源電壓: 1.4 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應商設備封裝: 8-SOIC
包裝: 管件
其它名稱: 800-2590-5
ICS830154AMI-08LF-ND
ICS830154AGI-08 REVISION A MARCH 29, 2010
5
2010 Integrated Device Technology, Inc.
ICS830154I-08 Data Sheet
OVER-VOLTAGE TOLERANT 1.5V, 1:4 FANOUT BUFFER
Table 4H. LVCMOS DC Characteristics, VDD = 1.5V ± 0.1V, TA = -40°C to 85°C
AC Electrical Characteristics
Table 5A. AC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has
been reached under these conditions.
NOTE: Characterized up to FOUT ≤ 150MHz.
NOTE 1: Measured from the VDD/2 of the input to VDD/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDD/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDD/2.
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VIH
Input High Voltage
0.65 * VDD
3.6
V
VIL
Input Low Voltage
-0.3
0.35 * VDD
V
IIH
Input High Current
CLK_IN
VDD = VIN = 1.6V
150
A
OE
VDD = VIN = 1.6V
5
A
IIL
Input Low Current
CLK_IN
VDD = 1.6V, VIN = 0V
-5
A
OE
VDD = 1.6V, VIN = 0V
-150
A
VOH
Output High Voltage
Q[4:1]
IOH = -4mA
0.75 * VDD
V
VOL
Output Low Voltage
Q[4:1]
IOL = 4mA
0.25 * VDD
V
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fOUT
Output Frequency
160
MHz
tpLH
Propagation Delay
(low to high transition); NOTE 1
0.7
1.45
ns
tpHL
Propagation Delay
(high to low transition); NOTE 1
0.7
1.45
ns
tPLZ, tPHZ
Disable Time
(active to high-impedance)
10
ns
tPZL, tPZH
Enable Time
(high-impedance to disable)
10
ns
tsk(o)
Output Skew; NOTE 2, 3
250
ps
tsk(pp)
Part-to-Part Skew; NOTE 2, 4
800
ps
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
25MHz, Integration Range:
12kHz - 5MHz
0.094
ps
tR / tF
Output Rise/Fall Time
10% to 90%
0.35
1.2
ns
odc
Output Duty Cycle
48
52
%
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