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參數(shù)資料
| 型號(hào)： | ICS83052AGILFT |
| 英文描述： | 2:1, SINGLE-ENDED MULTIPLEXER |
| 中文描述： | 2:1，單端復(fù)用器 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大小： | 178K |
| 代理商： | ICS83052AGILFT |
Integrated
Circuit
Systems, Inc.
83052AGI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 2, 2005
7
ICS83052I
2:1, S
INGLE
-E
NDED
M
ULTIPLEXER
A
DDITIVE
P
HASE
J
ITTER
Additive Phase Jitter (Random)
at 155.52MHz (12kHz - 20MHz)
= 0.18ps (typical)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise.
This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
As with most timing specifications, phase noise measure-
ments have issues. The primary issue relates to the limita-
tions of the equipment. Often the noise floor of the equipment
is higher than the noise floor of the device. This is illustrated
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a
dBc
value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
above. The device meets the noise floor of what is shown, but
can actually be lower. The phase noise is dependant on the
input source and measurement equipment.
O
FFSET
F
ROM
C
ARRIER
F
REQUENCY
(H
Z
)
S
H
O
Z
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS83052AGIT | 2:1, SINGLE-ENDED MULTIPLEXER |
| ICS83052I | 2:1, SINGLE-ENDED MULTIPLEXER |
| ICS83054AGI-01 | 4-BIT, 2 : 1, SINGLE-ENDED MULTIPLEXER |
| ICS83054I-01 | 4-BIT, 2 : 1, SINGLE-ENDED MULTIPLEXER |
| ICS83054AGIT | 4 : 1, SINGLE-ENDED MULTIPLEXER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS83052AGIT | 制造商:ICS 制造商全稱:ICS 功能描述:2:1, SINGLE-ENDED MULTIPLEXER |
| ICS83052I | 制造商:ICS 制造商全稱:ICS 功能描述:2:1, SINGLE-ENDED MULTIPLEXER |
| ICS83052I-01 | 制造商:ICS 制造商全稱:ICS 功能描述:2-BIT, 2 : 1, SINGLE-ENDED MULTIPLEXER |
| ICS83054AGI | 制造商:ICS 制造商全稱:ICS 功能描述:4 : 1, SINGLE-ENDED MULTIPLEXER |
| ICS83054AGI-01 | 制造商:ICS 制造商全稱:ICS 功能描述:4-BIT, 2 : 1, SINGLE-ENDED MULTIPLEXER |
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