參數(shù)資料
型號: ICS83115BRT
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘及定時
英文描述: 83115 SERIES, LOW SKEW CLOCK DRIVER, 16 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28
封裝: 9.90 X 3.90 MM, 1.70 MM HEIGHT, MO-137, SSOP-28
文件頁數(shù): 1/11頁
文件大?。?/td> 321K
代理商: ICS83115BRT
ICS83115
LOW SKEW, 1-TO-16
LVCMOS / LVTTL FANOUT BUFFER
83115BR
www.icst.com/products/hiperclocks.html
REV. B MARCH 3, 2006
1
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
The ICS83115 is a low skew, 1-to-16 LVCMOS/
LVTTL Fanout Buffer and a member of the
HiPerClockS family of High Performance Clock
Solutions from ICS. The ICS83115 single ended
clock input accepts LVCMOS or LVTTL input
levels. The ICS83115 operates at full 3.3V supply mode over
the commercial temperature range. Guaranteed output and
part-to-part skew characteristics make the ICS83115 ideal
for those clock distribution applications demanding well de-
fined performance and repeatability.
BLOCK DIAGRAM
PIN ASSIGNMENT
FEATURES
Sixteen LVCMOS/LVTTL outputs
One LVCMOS/LVTTL clock input
Maximum output frequency: 200MHz
All inputs are 5V tolerant
Output skew: 250ps (maximum)
Part-to-part skew: 800ps (maximum)
Additive phase jitter, RMS: 0.09ps (typical)
3.3V operating supply
0°C to 70°C ambient operating temperature
Available in both standard and lead-free RoHS compliant
packages
Industrial temperature information available upon request
ICS83115
28-Lead SSOP, 150mil
9.9mm x 3.9mm x 1.7mm body package
R Package
(Top View)
HiPerClockS
ICS
Q15
Q14
Q13
Q12
Q11
Q10
Q9
Q8
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
OE1
GND
OE0
V
DD
IN
4
OE1
Q0
Q1
Q2
VDD
Q3
Q4
GND
Q5
Q6
Q7
IN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OE2
Q15
Q14
Q13
VDD
Q12
Q11
GND
Q10
Q9
Q8
OE0
OE2
OE1
OE2
DATA SHEET
ICS83115
IDT / ICS LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER
ICS83115
1
LOW SKEW, 1-TO-16 LVCMOS /
LVTTL FANOUT BUFFER
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