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參數(shù)資料
| 型號： | ICS8402AK |
| 英文描述： | 350MHZ, CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER |
| 中文描述： | 350MHz頻段，水晶到的LVCMOS / LVTTL頻率合成器 |
| 文件頁數(shù)： | 2/15頁 |
| 文件大?。?/td> | 247K |
| 代理商： | ICS8402AK |
8402AY
www.icst.com/products/hiperclocks.html
REV. B OCTOBER 6, 2004
2
Integrated
Circuit
Systems, Inc.
ICS8402
350MH
Z
, C
RYSTAL
-
TO
-LVCMOS / LVTTL
F
REQUENCY
S
YNTHESIZER
put divider to a specific default state that will automatically
occur during power-up. The TEST output is LOW when op-
erating in the parallel input mode. The relationship between
the VCO frequency, the crystal frequency and the M divider
is defined as follows:
fVCO = fxtal x M
The M value and the required values of M0 through M8 are
shown in Table 3B, Programmable VCO Frequency Function
Table. Valid M values for which the PLL will achieve lock for a
25MHz reference are defined as 10
≤
M
≤
28. The frequency
out is defined as follows:
FOUT = fVCO = fxtal x M
Serial operation occurs when nP_LOAD is HIGH and
S_LOAD is LOW. The shift register is loaded by sampling
the S_DATA bits with the rising edge of S_CLOCK. The con-
tents of the shift register are loaded into the M divider and N
output divider when S_LOAD transitions from LOW-to-HIGH.
The M divide and N output divide values are latched on the
HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH,
data at the S_DATA input is passed directly to the M divider
and N output divider on each rising edge of S_CLOCK. The
serial mode can be used to program the M and N bits and
test bits T1 and T0. The internal registers T0 and T1 deter-
mine the state of the TEST output as follows:
NOTE: The functional description that follows describes op-
eration using a 25MHz crystal. Valid PLL loop divider values
for different crystal or input frequencies are defined in the
Input Frequency Characteristics, Table 5, NOTE 1.
The ICS8402 features a fully integrated PLL and therefore
requires no external components for setting the loop band-
width. A fundamental crystal is used as the input to the on-
chip oscillator. The output of the oscillator is fed into the phase
detector. A 25MHz crystal provides a 25MHz phase detector
reference frequency. The VCO of the PLL operates over a
range of 250MHz to 700MHz. The output of the M divider is
also applied to the phase detector.
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency by adjusting
the VCO control voltage. Note that for some values of M (either
too high or too low), the PLL will not achieve lock. The output of
the VCO is scaled by a divider prior to being sent to each of
the LVCMOS output buffers. The divider provides a 50% out-
put duty cycle.
The programmable features of the ICS8402 support two in-
put modes to program the M divider and N output divider.
The two input operational modes are parallel and serial. Fig-
ure 1 shows the timing diagram for each mode. In parallel
mode, the nP_LOAD input is initially LOW. The data on in-
puts M0 through M8 and N0 and N1 is passed directly to the
M divider and N output divider. On the LOW-to-HIGH transi-
tion of the nP_LOAD input, the data is latched and the M
divider remains loaded until the next LOW transition on
nP_LOAD or until a serial event occurs. As a result, the M
and N bits can be hardwired to set the M divider and N out-
F
UNCTIONAL
D
ESCRIPTION
T1
T0
TEST Output
0
0
LOW
0
1
Shift Register Output
1
0
Output of M divider
1
1
CMOS Fout
F
IGURE
1. P
ARALLEL
& S
ERIAL
L
OAD
O
PERATIONS
*NOTE:
The NULL timing slot must be observed.
Time
S
ERIAL
L
OADING
P
ARALLEL
L
OADING
M, N
t
S
t
H
t
S
t
H
t
S
T1
T0
*
NULL
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
N
N
S_CLOCK
S_DATA
S_LOAD
nP_LOAD
M0:M8, N0:N1
nP_LOAD
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ICS8402AKI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:350MHZ, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER |
| ICS8402AKIL | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:350MHZ, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER |
| ICS8402AKILF | 功能描述:IC FREQ SYNTHESIZER 32VFQFPN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™ 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應商設備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| ICS8402AKILFT | 功能描述:IC FREQ SYNTHESIZER 32VFQFPN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™ 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應商設備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| ICS8402AKIT | 功能描述:IC FREQ SYNTHESIZER 32VFQFPN RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™ 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應商設備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
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