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參數(shù)資料
| 型號： | ICS8421002AGI-01LFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 13/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FREQ SYNTHESIZER 20-TSSOP |
| 標準包裝： | 2,500 |
| 系列： | HiPerClockS™, FemtoClock™ |
| 類型： | 頻率合成器 |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS，LVTTL，晶體 |
| 輸出： | LVHSTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 170MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.375 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 8421002AGI-01LFT |
Micrel, Inc.
SY88149NDL
February 2012
8
M9999-020712-A
hbwhelp@micrel.com or (408) 955-1690
Detailed Description
The SY88149NDL is a high-sensitivity limiting post
amplifier which operates on a +3.3V power supply over
the industrial temperature range. Signals with data rates
up to 1.25Gbps and as small as 5mVpp can be amplified.
Depending on the LOS/SD SEL option, the SY88149NDL
can generate an SD or LOS output, and allow feedback to
the JAM input for output stability. LOS/SDLVL sets the
sensitivity of the input amplitude detection.
To satisfy the stringent timing requirements of the
GPON specifications, the signal detect circuit offers 5ns
SD assert (LOS deassert) time and the option to
deassert SD (assert LOS) using the /AUTO RESET or
manual RESET function. When /AUTO RESET is
enabled, SD deasserts/LOS asserts automatically within
120ns after the last high-to-low transition of the input
burst. When the /AUTORESET function is disabled, the
SD deassert/LOS assert time can be reset by using the
provided RESET pin.
Input Buffer
Figure 2 shows a simplified schematic of the input stage.
The high sensitivity of the input amplifier allows signals as
small as 5mVpp to be detected and amplified. The input
buffer can allow input signals as large as 1800mVPP. Input
signals are linearly amplified with a typically 48dB
differential voltage gain until the outputs reach 1500mVPP
(typical). Applications requiring the SY88149NDL to
operate with high-gain should have the upstream TIA
placed as close as possible to the SY88149NDL’s input
pins. This ensures the best performance of the device.
Output Buffer
The SY88149NDL’s LVPECL output buffer is designed
to drive 50 lines. The output buffer requires
appropriate termination for proper operation. An external
50 resistor to VCC – 2V for each output pin provides
this. Figure 3 shows a simplified schematic of the output
stage
Loss of Signal/Signal Detect
The SY88149NDL generates a chatter-free Signal-Detect
(SD) or Loss of Signal (LOS) LVTTL output, as shown in
Figure 4. A highly-sensitive signal detect circuit is used to
determine that the input amplitude is too small to be
considered a valid input. LOS asserts high if the input
amplitude falls below the threshold sets by LOS/SDLVL
and deasserts low otherwise. SD asserts high if the input
amplitude rises above threshold set by LOS/SDLVL and
deasserts low otherwise. LOS/SD can be fed back to the
JAM input to maintain output stability under the absence of
an invalid signal condition Typically, a
3dB to 4 dB
hysteresis is provided to minimize or prevent chattering.
LOS/SD Level Set
A programmable LOS/SD level pin (LOS/SDLVL) sets the
threshold of the input amplitude detection. Connecting
an external resistor between VCC and LOS/SDLVL sets
the voltage at LOS/SDLVL. This voltage ranges from VCC
to VREF. The external resistor creates a voltage divider
between VCC and VREF, as shown in Figure 5. Set the
LOS/SDLVL voltage closer to VREF or more sensitive
LOS/SD detection or closer to VCC for higher inputs.
Note that the SY88149NDL is designed for use in the
burst mode PON application, where every burst is
preceded with several bytes of a 1010 PON preamble
pattern. Therefore, the SD Assert (LOS De-assert) is
designed to trigger on the first few bits of this preamble
pattern and therefore the SD/LOS thresholds outlined in
the AC electrical characteristics are specified using this
preamble pattern. Once the SD is Asserted (LOS De-
asserted), the SD is De-asserted (LOS Asserted) only
by the application of a Manual RESET or an AUTO
RESET if the Auto Reset is activated, The auto reset
asserts a reset approximately 120 nS after the last
negative going transition of the data as explained earlier.
Noise Discriminator
The noise discriminator feature is intended for the high-
gain burst-mode TIAs where noise can trigger a false
LOS deassert or SD assert while no input data is
present. The noise discriminator will filter input data
through a series of specialized circuitry that will only
trigger LOS/SD on the rising edge of a valid PON 1.244
Gbps preamble bit stream (10101). The SY88149NDL
noise discriminator is designed to accept a 1.244 Gbps
+/-300 MBPS preamble burst. Any other bit pattern will
be rejected. If this part is used at any other data rate, the
Noise Discriminator should be disengaged. The noise
discriminator, implemented in the edge detector circuit,
can be selected or bypassed by selecting the proper
resistor value using the settings at LOS/SDSEL pin.
Refer to the “Truth Table for SD/LOS select and Noise
Discriminator function” found on page 2 for more
detailed information.
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| ICS8421002AGILF | 功能描述:IC FREQ SYNTHESIZER 20-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™, FemtoClock™ 標準包裝:27 系列:Precision Edge® 類型:頻率合成器 PLL:是 輸入:PECL，晶體 輸出:PECL 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/是 頻率 - 最大:800MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 5.25 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC 包裝:管件 |
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