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參數(shù)資料
| 型號(hào)： | ICS8421002I-01 |
| 英文描述： | FEMTOCLOCKS⑩ CRYSTAL-TO-HSTL FREQUENCY SYNTHESIZER |
| 中文描述： | FEMTOCLOCKS⑩晶體對(duì)HSTL頻率合成器 |
| 文件頁數(shù)： | 1/13頁 |
| 文件大?。?/td> | 200K |
| 代理商： | ICS8421002I-01 |
8421002AGI-01
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 6, 2006
1
Integrated
Circuit
Systems, Inc.
ICS8421002I-01
F
EMTO
C
LOCKS
C
RYSTAL
-
TO
-
HSTL F
REQUENCY
S
YNTHESIZER
G
ENERAL
D
ESCRIPTION
The ICS8421002I-01 is a 2 output HSTL
Synthesizer optimized to generate Ethernet
reference clock frequencies and is a member of
the HiPerClocks
TM
family of high performance
clock solutions from ICS. Using a 25MHz,
18pF parallel resonant crystal, the following frequencies
can be generated based on the 2 frequency select pins
(F_SEL[1:0]): 156.25MHz, 125MHz and 62.5MHz. The
ICS8421002I-01 uses ICS’ 3
rd
generation low phase
noise VCO technology and can achieve 1ps or lower typi-
cal rms phase jitter, easily meeting Ethernet jitter
requirements. The ICS8421002I-01 is packaged in a small
20-pin TSSOP package.
F
EATURES
Two HSTL outputs (VOHmax = 1.5V)
Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
Supports the following output frequencies: 156.25MHz,
125MHz, 62.5MHz
VCO range: 560MHz - 680MHz
RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.44ps (typical)
Power supply modes:
Core/Output
3.3V/1.8V
2.5V/1.8V
-40°C to 85°C ambient operating temperature
Available in both standard and lead-free RoHS compliant
packages
HiPerClockS
ICS
1
0
1
0
Phase
Detector
VCO
M = 25 (fixed)
F_SEL[1:0]
0 0 ÷4
(default)
0 1 ÷5
1 0 ÷10
1 1
Not Used
2
OSC
ICS8421002I-01
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm
package body
G Package
Top View
B
LOCK
D
IAGRAM
y
c
n
e
u
)
R
q
e
z
r
F
H
t
u
5
p
t
u
O
M
2
1
L
E
S
_
F
0
L
E
S
_
F
r
e
d
D
u
V
5
2
5
2
5
2
M
e
r
e
d
D
u
V
4
5
1
d
e
N
e
0
0
1
1
0
1
0
1
5
2
5
2
1
5
6
u
t
n
1
5
0
s
u
t
n
d
e
s
F
REQUENCY
S
ELECT
F
UNCTION
T
ABLE
F_SEL[1:0]
nPLL_SEL
REF_CLK
XTAL_IN
XTAL_OUT
nXTAL_SEL
MR
Q0
nQ0
Q1
nQ1
Pulldown
Pulldown
25MHz
Pulldown
Pulldown
Pulldown
nc
V
DDO
Q0
nQ0
MR
nPLL_SEL
nc
V
DDA
F_SEL0
V
DD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DDO
Q1
nQ1
GND
V
DD
nXTAL_SEL
REF_CLK
XTAL_IN
XTAL_OUT
F_SEL1
P
IN
A
SSIGNMENT
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