參數(shù)資料
型號(hào)： ICS843002CY-31T
英文描述： 700MHZ FEMTOCLOCKS⑩ VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR
中文描述： ⑩VCXO的700MHz的FEMTOCLOCKS基于頻率轉(zhuǎn)換和抖動(dòng)衰減器
文件頁(yè)數(shù)： 21/27頁(yè)
文件大?。?/td> 274K
代理商： ICS843002CY-31T
843002CY-31
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 22, 2005
21
Integrated
Circuit
Systems, Inc.
ICS843002-31
700MH
Z
F
EMTO
C
LOCKS
VCXO B
ASED
F
REQUENCY
T
RANSLATOR
AND
J
ITTER
A
TTENUATOR
PRELIMINARY
F
IGURE
5. S
INGLE
-E
NDED
C
LOCK
I
NPUT
I
NTERFACE
3.3V
CLK
nCLK
3.3V
51k
51k
51k
(no connection)
Differential
Input Stage
LVTTL
or LVCMOS
Logic Output
Series
Termination
Optional
Series
Filter
Resistor
nCLK0
CLK0
Internal Device Circuitry
External Circuitry
D
IFFERENTIAL
C
LOCK
I
NPUT
C
IRCUIT
U
SING
THE
D
IFFERENTIAL
I
NTERFACE
FOR
S
INGLE
-E
NDED
C
LOCKS
The differential interface (CLK0/nCLK0) can be used as a
third single-ended input to support an LVCMOS or LVTTL
clock driver. The clock input is connected to the CLK0 input
pin, and the nCLK0 pin is left unconnected. To help reduce
interference with the internal VCO circuits, an external
resistor can be placed in series with the clock signal near
the CLK0 input pint. Combined with the input pin capaci-
tance, this resistor acts as a low pass signal filter. The
typical value of this optional series filter resistor is 100
Ω
.
This will lower both the amplitude and edge rate of the
clock input signal. In the case of a very short clock trace a
series termination register may not be needed.
I
NPUTS
:
C
RYSTAL
I
NPUT
:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating.
Though not required, but for additional protection, a 1k
Ω
resistor can be tied from XTAL_IN to ground.
CLK I
NPUT
:
For applications not requiring the use of a clock input, it can
be left floating. Though not required, but for additional
protection, a 1k
Ω
resistor can be tied from the CLK input to
ground.
CLK/nCLK I
NPUT
:
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required,
but for additional protection, a 1k
Ω
resistor can be tied from
CLK to ground.
LVCMOS C
ONTROL
P
INS
:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
Ω
resistor can be used.
R
ECOMMENDATIONS
FOR
U
NUSED
I
NPUT
AND
O
UTPUT
P
INS
O
UTPUTS
:
LVCMOS O
UTPUT
:
All unused LVCMOS output can be left floating. We
recommend that there is no trace attached.
LVPECL O
UTPUT
All unused LVPECL outputs can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or
terminated.
相關(guān)PDF資料
PDF描述
ICS843002AGI-01 FEMTOCLOCKS-TM CRYSTAL-TO- 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
ICS843002AGI-01LF FEMTOCLOCKS-TM CRYSTAL-TO- 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
ICS843002AGI-01LFT FEMTOCLOCKS-TM CRYSTAL-TO- 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
ICS843002AGI-01T FEMTOCLOCKS-TM CRYSTAL-TO- 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
ICS843002I-01 FEMTOCLOCKS-TM CRYSTAL-TO- 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ICS843002I 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS-TM CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
ICS843002I-01 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS-TM CRYSTAL-TO- 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
ICS843002I-40 制造商:ICS 制造商全稱:ICS 功能描述:175MHZ, FEMTOCLOCKS-TM VCXO BASED SONET/SDH JITTER ATTENUATOR
ICS843002I-41 制造商:ICS 制造商全稱:ICS 功能描述:700MHz, FEMTOCLOCKS-TM VCXO BASED SONET/SDH JITTER ATTENUATOR
ICS843002I-72 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:FEMTOCLOCKS⑩ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
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