參數(shù)資料
型號(hào): ICS843004AGILFT
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 3/19頁(yè)
文件大小: 0K
描述: IC SYNTHESIZER LVPECL 24-TSSOP
標(biāo)準(zhǔn)包裝: 2,500
系列: HiPerClockS™, FemtoClock™
類型: 頻率合成器
PLL: 帶旁路
輸入: 晶體
輸出: LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 1:4
差分 - 輸入:輸出: 無(wú)/是
頻率 - 最大: 226.66MHz
除法器/乘法器: 是/無(wú)
電源電壓: 2.375 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 24-TSSOP
包裝: 帶卷 (TR)
其它名稱: 843004AGILFT
ICS843004AGI REVISION A FEBRUARY 19, 2010
11
2010 Integrated Device Technology, Inc.
ICS843004I Data Sheet
FEMTOCLOCK LVCMOS/CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 4A and 4B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
Figure 4A. 3.3V LVPECL Output Termination
Figure 4B. 3.3V LVPECL Output Termination
3.3V
V
CC - 2V
R1
50
R2
50
RTT
Z
o = 50
Z
o = 50
+
_
RTT =
* Z
o
1
((V
OH + VOL) / (VCC – 2)) – 2
3.3V
LVPECL
Input
R1
84
R2
84
3.3V
R3
125
R4
125
Z
o = 50
Z
o = 50
LVPECL
Input
3.3V
+
_
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ICS843004AGT 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS⑩ LVCMOS/CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
ICS843004AI01 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS-TM CRYSTAL-TO- 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER