IDT / ICS 3.3V, 2.5V LVPECL CLOCK GENERAT" />
參數(shù)資料
型號(hào): ICS843023AGILF
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 10/12頁(yè)
文件大?。?/td> 0K
描述: IC CLK GEN 1GIG LVPECL 8-TSSOP
特色產(chǎn)品: Gigabit Ethernet Clock Synthesizer
標(biāo)準(zhǔn)包裝: 96
系列: HiPerClockS™, FemtoClock™
類(lèi)型: 時(shí)鐘/頻率合成器,時(shí)鐘發(fā)生器
PLL:
輸入: 晶體
輸出: LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 無(wú)/是
頻率 - 最大: 320MHz
除法器/乘法器: 是/無(wú)
電源電壓: 2.375 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 8-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 8-TSSOP
包裝: 管件
其它名稱(chēng): 800-1134
800-1134-5
800-1134-ND
843023AGILF
IDT / ICS 3.3V, 2.5V LVPECL CLOCK GENERATOR
7
ICS843023AGI REV. B JANUARY 9, 2007
ICS843023I
FEMTOCLOCKS CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR
APPLICATION INFORMATION
FIGURE 1. CRYSTAL INPUt INTERFACE
CRYSTAL INPUT INTERFACE
The ICS843023I has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 1 below were determined using a 25MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error. The
optimum C1 and C2 values can be slightly adjusted for different
board layouts.
C1
33p
X1
18pF Parallel Crystal
C2
22p
XTAL_OUT
XTAL_IN
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS
signal through an AC couple capacitor. A general interface
diagram is shown in
Figure 2. The XTAL_OUT pin can be left
floating. The input edge rate can be as slow as 10ns. For
LVCMOS inputs, it is recommended that the amplitude be
reduced from full swing to half swing in order to prevent signal
interference with the power rail and to reduce noise. This
configuration requires that the output impedance of the driver
FIGURE 2. General Diagram for LVCMOS Driver to XTAL Input Interface
(Ro) plus the series resistance (Rs) equals the transmission
line impedance. In addition, matched termination at the crystal
input will attenuate the signal in half. This can be done in one
of two ways. First, R1 and R2 in parallel should equal the
transmission line impedance. For most 50
applications, R1
and R2 can be 100
. This can also be accomplished by remov-
ing R1 and making R2 50
.
R2
Zo = 50
VDD
Ro
Zo = Ro + Rs
R1
VDD
XTAL_IN
XTAL_OUT
.1uf
Rs
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