FEMTOCLOCK
參數(shù)資料
型號: ICS843051AGLF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 5/17頁
文件大小: 0K
描述: IC CLK GEN GIG ETH LVPECL 8TSSOP
特色產(chǎn)品: Gigabit Ethernet Clock Synthesizer
標(biāo)準(zhǔn)包裝: 96
系列: HiPerClockS™, FemtoClock™
類型: 時鐘/頻率合成器,時鐘發(fā)生器
PLL:
輸入: 晶體
輸出: LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 無/是
頻率 - 最大: 161.13MHz
除法器/乘法器: 是/無
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 8-TSSOP
包裝: 管件
產(chǎn)品目錄頁面: 1250 (CN2011-ZH PDF)
其它名稱: 800-1136
800-1136-5
800-1136-ND
843051AGLF
ICS843051AG REVISION A OCTOBER 13, 2010
13
2010 Integrated Device Technology, Inc.
ICS843051 Data Sheet
FEMTOCLOCK CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pair.
LVPECL output driver circuit and termination are shown in Figure 6.
Figure 6. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of
VCC – 2V.
For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V
(VCC_MAX – VOH_MAX) = 0.9V
For logic low, VOUT = VOL_MAX = VCC_MAX – 1.7V
(VCC_MAX – VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) =
[(2V – 0.9V)/50
] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) =
[(2V – 1.7V)/50
] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
V
OUT
V
CC
V
CC - 2V
Q1
RL
50
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參數(shù)描述
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