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參數(shù)資料
| 型號： | ICS8430DY-11LF |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 700 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 196K |
| 代理商： | ICS8430DY-11LF |
8430DY-11
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 10, 2003
2
Integrated
Circuit
Systems, Inc.
ICS8430-11
700MHZ, LOW JITTER
CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
NOTE: The functional description that follows describes operation using a 16MHz crystal. Valid PLL loop divider values for
different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 5, NOTE 1.
The ICS8430-11 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth.
A parallel-resonant, fundamental crystal is used as the input to the on-chip oscillator. The output of the oscillator is divided by
16 prior to the phase detector. With a 16MHz crystal, this provides a 1MHz reference frequency. The VCO of the PLL operates
over a range of 200MHz to 700MHz. The output of the M divider is also applied to the phase detector.
The phase detector and the M divider force the VCO output frequency to be 2M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the
VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output duty cycle.
The programmable features of the ICS8430-11 support two input modes to program the M divider and N output divider.
The two input operational modes are parallel and serial.
Figure 1 shows the timing diagram for each mode. In parallel mode,
the nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0 through N2 is passed directly to the M divider
and N output divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains
loaded until the next LOW transition on nP_LOAD or until a serial event occurs. As a result, the M and N bits can be hardwired
to set the M divider and N output divider to a specific default state that will automatically occur during power-up. The TEST
output is LOW when operating in the parallel input mode. The relationship between the VCO frequency, the crystal frequency
and the M divider is defined as follows:
The M value and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function Table.
Valid M values for which the PLL will achieve lock for a 16MHz reference are defined as 100
≤ M ≤ 350. The frequency out is
defined as follows:
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N output divider when
S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-to-LOW transition
of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and N output divider on each
rising edge of S_CLOCK. The serial mode can be used to program the M and N bits and test bits T1 and T0. The internal
registers T0 and T1 determine the state of the TEST output as follows:
FUNCTIONAL DESCRIPTION
N
fout = fVCO =
16
2M
fxtal x
N
16
fVCO =
fxtal x 2M
T1
T0
TEST Output
0
LOW
0
1
S_Data, Shift Register Input
1
0
Output of M divider
1
CMOS Fout
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
Time
SERIAL LOADING
PARALLEL LOADING
M, N
t
S
t
H
t
S
t
H
t
S
T1
T0
N2
N 1
N 0
M8
M7
M6
M5
M4
M3
M2
M1
M0
S_CLOCK
S_DATA
S_LOAD
nP_LOAD
M0:M8, N0:N2
nP_LOAD
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| ICS8430I-61 | 制造商:ICS 制造商全稱:ICS 功能描述:500MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER |
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