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參數(shù)資料
| 型號： | ICS843101AG-312 |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 312.5 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| 封裝： | 4.40 X 5 MM, 0.92 MM HEIGHT, MO-153, TSSOP-16 |
| 文件頁數(shù)： | 1/14頁 |
| 文件大?。?/td> | 631K |
| 代理商： | ICS843101AG-312 |
843101AG-312
www.icst.com/products/hiperclocks.html
OCTOBER 18, 2005
1
Integrated
Circuit
Systems, Inc.
ICS843101-312
FEMTOCLOCKSCRYSTAL-TO-LVPECL
312.5MHZ FREQUENCY MARGINING SYNTHESIZER
ADVANCE INFORMATION
GENERAL DESCRIPTION
The ICS843101-312 is a low phase-noise
frequency margining synthesizer with fre-
quency margining capability and is a member of
the HiPerClockS family of high performance
clock solutions from ICS. In the default mode,
the device nominally generates a 312.5MHz LVPECL output
clock signal from a 25MHz crystal input. There is also a
frequency margining mode available where the device can
be programmed, using the serial interface, to vary the
output frequency up or down from nominal in 2% steps.
The ICS843101-312 is provided in a 16-pin TSSOP.
FEATURES
One 312.5MHz nominal LVPECL output
Selectable crystal oscillator interface designed for 25MHz,
18pF parallel resonant crystal or LVCMOS single-ended
input
Output frequency can be varied in 2% steps ± from nominal
VCO range: 560MHz - 690MHz
RMS phase jitter @ 312.5MHz, using a 25MHz crystal
(1.875MHz-20MHz): <1ps (typical) design target
Output supply modes
Core/Output
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
0°C to 70°C ambient operating temperature
Available in both standard and lead-free RoHS-complaint
packages
HiPerClockS
ICS
PIN ASSIGNMENT
The Advance Information presented herein represents a product currently in design or being considered for design. The noted characteristics are
design targets. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
VEE
S_LOAD
S_DATA
S_CLOCK
SEL
OE
VCCA
VCC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
MODE
VCCO
Q
nQ
VEE
CLK
XTAL_OUT
XTAL_IN
ICS843101-312
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm
package body
G Package
Top View
BLOCK DIAGRAM
1
0
Phase
Detector
VCO
560 - 690MHz
÷ M
OSC
÷ N
÷ P
Serial Control
Q
nQ
Pullup
Pulldown
OE
CLK
SEL
S_CLOCK
S_DATA
S_LOAD
MODE
XTAL_IN
XTAL_OUT
Pulldown
25MHz
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS843101AGI-312T | 312.5 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| ICS843101AGI-312LFT | 312.5 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| ICS843101AGI-312LF | 312.5 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| ICS843101IAG-100LFT | 100 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| ICS843101IAG-100LF | 100 MHz, OTHER CLOCK GENERATOR, PDSO16 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS843101AG-312LF | 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER |
| ICS843101AG-312LFT | 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER |
| ICS843101AG-312T | 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER |
| ICS843101AGI-100LF | 功能描述:IC SYNTHESIZER 100MHZ 16-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™, FemtoClock™ 標(biāo)準(zhǔn)包裝:27 系列:Precision Edge® 類型:頻率合成器 PLL:是 輸入:PECL，晶體 輸出:PECL 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/是 頻率 - 最大:800MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 5.25 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC 包裝:管件 |
| ICS843101AGI-100LFT | 功能描述:IC SYNTHESIZER 100MHZ 16-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™, FemtoClock™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
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