- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67690 > ICS843101IAG-100LF (INTEGRATED DEVICE TECHNOLOGY INC) 100 MHz, OTHER CLOCK GENERATOR, PDSO16 PDF資料下載
參數(shù)資料
| 型號： | ICS843101IAG-100LF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產生/分配 |
| 英文描述： | 100 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| 封裝： | 4.40 X 5 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-16 |
| 文件頁數(shù)： | 3/17頁 |
| 文件大?。?/td> | 435K |
| 代理商： | ICS843101IAG-100LF |
843101AGI-100
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 20, 2005
11
Integrated
Circuit
Systems, Inc.
ICS843101I-100
FEMTOCLOCKS CRYSTAL-TO-LVPECL
100MHZ FREQUENCY MARGINING SYNTHESIZER
PRELIMINARY
TERMINATION FOR 3.3V LVPECL OUTPUT
V
CC - 2V
50
Ω
50
Ω
RTT
Z
o = 50Ω
Z
o = 50Ω
FOUT
FIN
RTT =
Z
o
1
((V
OH + VOL) / (VCC – 2)) – 2
3.3V
125
Ω
125
Ω
84
Ω
84
Ω
Z
o = 50Ω
Z
o = 50Ω
FOUT
FIN
The clock layout topology shown below is a typical ter-
mination for LVPECL outputs. The two different layouts
mentioned are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs
that generate ECL/LVPECL compatible outputs. There-
fore, terminating resistors (DC current path to ground)
or current sources must be used for functionality. These
FIGURE 4B. LVPECL OUTPUT TERMINATION
FIGURE 4A. LVPECL OUTPUT TERMINATION
outputs are designed to drive 50
Ω transmission lines.
Matched impedance techniques should be used to maxi-
mize operating frequency and minimize signal distor-
tion. Figures 4A and 4B show two different layouts which
are recommended only as guidelines. Other suitable
clock layouts may exist and it would be recommended
that the board designers simulate to guarantee compat-
ibility across all printed circuit and clock component pro-
cess variations.
INPUTS:
CRYSTAL INPUT:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating. Though
not required, but for additional protection, a 1k
Ω resistor can be
tied from XTAL_IN to ground.
CLK INPUT:
For applications not requiring the use of the test clock, it can be
left floating. Though not required, but for additional protection, a
1k
Ω resistor can be tied from the CLK input to ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
Ω resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
LVPECL OUTPUT
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
相關PDF資料 |
PDF描述 |
|---|---|
| ICS84314AY-02LF | 700 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| ICS84314AYLFT | 350 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| ICS84314AYLF | 350 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| ICS84314AY | 350 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| ICS84314AYLFT | 350 MHz, OTHER CLOCK GENERATOR, PQFP32 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ICS843101IAG-100LFT | 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS? CRYSTAL-TO-LVPECL 100MHZ FREQUENCY MARGINING SYNTHESIZER |
| ICS843101IAG-100T | 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS? CRYSTAL-TO-LVPECL 100MHZ FREQUENCY MARGINING SYNTHESIZER |
| ICS843-106 | 制造商:ICS 制造商全稱:ICS 功能描述:106.25MHZ, LVCMOS, LVPECL DUAL OUTPUT OSCILLATOR |
| ICS8431-11 | 制造商:ICS 制造商全稱:ICS 功能描述:255MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER |
| ICS8431-21 | 制造商:ICS 制造商全稱:ICS 功能描述:350MHZ, LOW JITTER, CRYSTAL OSCILLATOR-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
發(fā)布緊急采購，3分鐘左右您將得到回復。