參數(shù)資料
型號: ICS843204AGILFT
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 1/16頁
文件大?。?/td> 0K
描述: IC SYNTHESIZER LVPECL 48-TSSOP
標(biāo)準(zhǔn)包裝: 1,000
系列: HiPerClockS™, FemtoClock™
類型: 頻率合成器
PLL:
輸入: LVCMOS,LVTTL,晶體
輸出: LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 4:4
差分 - 輸入:輸出: 無/是
頻率 - 最大: 156.25MHz
除法器/乘法器: 是/無
電源電壓: 2.97 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-TFSOP(0.240",6.10mm 寬)
供應(yīng)商設(shè)備封裝: 48-TSSOP
包裝: 帶卷 (TR)
其它名稱: 843204AGILFT
FEMTOCLOCK CRYSTAL-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
ICS843204I
IDT / ICS 3.3V LVPECL FREQUENCY SYNTHESIZER
1
ICS843204AGI REV. A MARCH 18, 2009
PLL
OSC
÷4
OSC
25MHz
19.44MHz
PLL
÷4
622.08MHz
155.52MHz
625MHz
156.25MHz
0
1
0
1
0
1
0
1
OEA0
SELA0
OEA1
SELA1
OEB0
SELB0
OEB1
SELB0
QA0
nQA0
QA1
nQA1
QB0
nQB0
QB1
nQB1
nPLL_BYPASS_A
IN_SELA
CLK0
XTAL_IN0
XTAL_OUT0
nPLL_BYPASS_B
IN_SELB
CLK1
XTAL_IN1
XTAL_OUT1
Pullup
Pulldown
GENERAL DESCRIPTION
The ICS843204I is a 4 output LVPECL Synthesizer
optimized to generate Gigabit Ethernet and SONET
reference clock frequencies and is a member of the
HiPerClocksTM family of high performance clock
solutions from IDT. Using a 19.44MHz and 25MHz,
18pF parallel resonant crystal, 155.52MHz and 156.25MHz
frequencies can be generated. The ICS843204I uses IDT’s
FemtoClockTM low phase noise VCO technology and can achieve
1ps or lower typical RMS phase jitter. The ICS843204I is pack-
aged in a 48-pin TSSOP package.
FEATURES
Four 3.3V LVPECL outputs
Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
Supports the following output frequencies: 155.52MHz
and 156.25MHz
VCO range: 560MHz - 680MHz
RMS phase jitter @ 155.52MHz, using a 19.44MHz crystal
(12kHz - 20MHz): 0.98ps (typical)
RMS phase jitter @ 156.25MHz, using a 19.44MHz crystal
(1.875MHz - 20MHz): 0.52ps (typical)
Full 3.3V supply mode
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
HiPerClockS
ICS
PIN ASSIGNMENT
ICS843204I
48 Lead TSSOP
6.1mm x 12.5mm x 0.925mm
package body
G Package
Top View
nQA1
QA1
nQA0
QA0
nc
VCCO_A
SELA1
SELA0
nPLL_BYPASS_A
nc
XTAL_IN1
XTAL_OUT1
CLK1
IN_SEL_B
nPLL_BYPASS_B
VCCO_B
nc
QB0
nQB0
QB1
nQB1
IN_SEL_A
CLK0
XTAL_IN0
XTAL_OUT0
nc
VEE
OEA0
OEA1
VCC
VCCA_A
nc
SELB0
VEE
OEB0
OEB1
VCC
SELB1
VCCA_B
nc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
BLOCK DIAGRAM
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