參數(shù)資料
型號: ICS843207CY-350LFT
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘產(chǎn)生/分配
英文描述: 375 MHz, OTHER CLOCK GENERATOR, PQFP48
封裝: 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026, LQFP-48
文件頁數(shù): 9/16頁
文件大?。?/td> 266K
代理商: ICS843207CY-350LFT
IDT / ICS LVPECL FREQUENCY MARGINING SYNTHESIZER
2
ICS843207CY-350 REV. A DECEMBER 3, 2007
ICS843207-350
FEMTOCLOCKS CRYSTAL-TO-LVPECL 350MHZ FREQUENCY MARGINING SYNTHESIZER
PRELIMINARY
FUNCTIONAL DESCRIPTION
The ICS843207-350 features a fully integrated PLL and
therefore requires no external components for setting the loop
bandwidth. A 14MHz fundamental crystal is used as the input
to the on chip oscillator. The output of the oscillator is fed into
the pre-divider. In frequency margining mode, the 14MHz
crystal frequency is divided by 2 and a 7MHz reference
frequency is applied to the phase detector. The VCO of the
PLL operates over a range of 620MHz to 750MHz. The output
of the M divider is also applied to the phase detector. The
default mode for the ICS843207-350 is a nominal VCO
frequency of 700MHz with each output configurable to divide
by 2, 4 or 8. The nominal output frequency can be changed by
placing the device into the margining mode using the mode pin
and using the margin pin to change the M feedback divider.
Frequency margining mode operation occurs when the MODE
input is HIGH. The phase detector and the M divider force the
VCO output frequency to be M times the reference frequency
by adjusting the VCO control voltage. The output of the VCO is
scaled by an output divider prior to being sent to the LVPECL
output buffer. The divider provides a 50% output duty cycle.
The relationship between the crystal input frequency, the M
divider, the VCO frequency and the output frequency is provided
in Table 1A. When changing back from frequency margining
mode to nominal mode, the device will return to the default
nominal configuration described above.
TABLE 1A. FREQUENCY SELECT FUNCTION TABLE
TABLE 1B. FREQUENCY MARGIN FUNCTION TABLE
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