FEMTOCLOCK CRYSTAL-TO-LVDS CLOCK GENERATOR IDT / ICS LVDS CLOCK GEN" />
參數(shù)資料
型號: ICS843251AGI-14LFT
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 14/15頁
文件大?。?/td> 0K
描述: IC CLK GEN ETHERNET 25MHZ 8TSSOP
標(biāo)準(zhǔn)包裝: 2,500
系列: HiPerClockS™, FemtoClock™
類型: 時鐘發(fā)生器
PLL:
輸入: 晶體
輸出: LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 無/是
頻率 - 最大: 170MHz
除法器/乘法器: 是/是
電源電壓: 2.375 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 8-TSSOP
包裝: 帶卷 (TR)
ICS844251-14
FEMTOCLOCK CRYSTAL-TO-LVDS CLOCK GENERATOR
IDT / ICS LVDS CLOCK GENERATOR
8
ICS844251BG-14 REV. A NOVEMBER 19, 2012
Parameter Measurement Information, continued
DIFFERENTIAL OUTPUT VOLTAGE SETUP
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter perform-
ance, power supply isolation is required. The ICS844251-14
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD and VDDA should
be individually connected to the power supply plane through vias,
and 0.01F bypass capacitors should be used for each pin. Figure
1 illustrates this for a generic VDD pin and also shows that VDDA
requires that an additional 10
resistor along with a 10F bypass
capacitor be connected to the VDDA pin.
Figure 1. Power Supply Filtering
Crystal Input Interface
The ICS844251-14 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2 below were determined using a 25MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error. The
optimum C1 and C2 values can be slightly adjusted for different
board layouts.
Figure 2. Crystal Input Interface
-
100
out
DC Input
V
DD
LVDS
VDD
VDDA
3.3V or 2.5V
10
Ω
10F
.01F
XTAL_IN
XTAL_OUT
X1
18pF Parallel Crystal
C1
27pF
C2
27pF
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