IDT / ICS 3.3V, 2.5V LVPECL CLOCK GENERATOR
10
ICS843251BGI-12 REV. A NOVEMBER 19, 2012
ICS843251I-12
FEMTOCLOCK
CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR
VCC
VCCA
C4
10uF
C5
0.01u
Zo = 50 Ohm
R3
133
To Logic
Input
pins
Zo = 50 Ohm
VCC
Set Logic
Input to
'0'
FREQ_SEL
VCC=3.3V
C1
27pF
C3
0.01u
1 8 p F
Q
Zo = 50 Ohm
RD1
Not Install
R1
10
XTAL_IN
R7
50
Optional
Y-Termination
To Logic
Input
pins
XTAL_OUT
3.3V
X1
25MHz
RD2
1K
VCC
U1
1
2
3
4
8
7
6
5
VCCA
VEE
XTAL_OUT
XTAL_IN
VCC
Q
nQ
FREQ_SEL
R2
133
Logic Control Input Examples
RU2
Not Install
R5
82.5
RU1
1K
nQ
C2
27pF
R4
82.5
R8
50
Zo = 50 Ohm
+
-
R6
50
Set Logic
Input to
'1'
+
-
SCHEMATIC EXAMPLE
Figure 6 shows an example of ICS843251I-12 application schematic.
In this example, the device is operated at V
CC
= 3.3V. The 18pF parallel
resonant 25MHz crystal is used. The C1 = 27pF and C2 = 27pF are
recommended for frequency accuracy. For different board layout, the
C1 and C2 may be slightly adjusted for optimizing frequency accuracy.
Two examples of LVPECL terminations are shown in this schematic.
Additional termination approaches are shown in the LVPECL
Termination Application Note.
FIGURE 6. ICS843251I-12 SCHEMATIC EXAMPLE