參數(shù)資料
型號: ICS843251BGI-15LFT
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 15/16頁
文件大?。?/td> 0K
描述: IC CLK GEN ETHERNET 25MHZ 8TSSOP
標(biāo)準(zhǔn)包裝: 2,500
系列: HiPerClockS™, FemtoClock™
類型: 時鐘發(fā)生器
PLL:
輸入: 晶體
輸出: LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 無/是
頻率 - 最大: 750MHz
除法器/乘法器: 是/是
電源電壓: 2.375 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 8-TSSOP
包裝: 帶卷 (TR)
ICS843251I-15
FEMTOCLOCKCRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR
IDT / ICS 3.3V, 2.5V LVPECL CLOCK GENERATOR
8
ICS843S51BGI-15 REV. A NOVEMBER 2, 2012
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal
distortion. Figures 4A and 4B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and
clock component process variations.
Figure 4A. 3.3V LVPECL Output Termination
Figure 4B. 3.3V LVPECL Output Termination
3.3V
V
CC - 2V
R1
50
Ω
R2
50
Ω
RTT
Z
o = 50Ω
Z
o = 50Ω
+
_
RTT =
* Z
o
1
((V
OH + VOL) / (VCC – 2)) – 2
3.3V
LVPECL
Input
R1
84
Ω
R2
84
Ω
3.3V
R3
125
Ω
R4
125
Ω
Z
o = 50Ω
Z
o = 50Ω
LVPECL
Input
3.3V
+
_
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ICS843251BGI-15T 制造商:Integrated Device Technology Inc 功能描述:IC SYNTHESIZER LVPECL 8TSSOP
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