參數(shù)資料
型號: ICS84329BM-01LFT
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 6/21頁
文件大?。?/td> 0K
描述: IC SYNTHESIZER 700MHZ 28-SOIC
標準包裝: 1,000
系列: HiPerClockS™
類型: 頻率合成器
PLL:
輸入: 晶體
輸出: LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 無/是
頻率 - 最大: 700MHz
除法器/乘法器: 是/無
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
供應商設(shè)備封裝: 28-SOIC
包裝: 帶卷 (TR)
其它名稱: 84329BM-01LFT
ICS84329B-01
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
IDT / ICS LVPECL FREQUENCY SYNTHESIZER
14
ICS84329BM-01 REV. C AUGUST 19, 2013
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS84329B-01.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS84329B-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 140mA = 485mW
Power (outputs)MAX = 30mW/Loaded Output pair
Total Power_MAX (3.3V, with all outputs switching) = 485mW + 30mW = 515mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature is 125°C.
The equation for Tj is as follows: Tj =
JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA must be used. Assuming a moderate
air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 31.1°C/W per Table 8A below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.515W * 31.1°C/W = 86°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (multi-layer).
Table 8A. Thermal Resistance JA for 28 Lead PLCC, Forced Convection
Table 8B. Thermal Resistance JA for 28 Lead SOIC, Forced Convection
JA by Velocity
Linear Feet per Minute
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
37.8°C/W
31.1°C/W
28.3°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
JA by Velocity
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
76.2°C/W
60.8°C/W
53.2°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
46.2°C/W
39.7°C/W
36.8°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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