參數(shù)資料
型號(hào)： ICS8432CY-111LF
元件分類(lèi)： 時(shí)鐘及定時(shí)
英文描述： PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封裝： 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32
文件頁(yè)數(shù)： 5/17頁(yè)
文件大小： 276K
代理商： ICS8432CY-111LF
8432CY-111
www.icst.com/products/hiperclocks.html
REV. B MARCH 3, 2004
13
Integrated
Circuit
Systems, Inc.
ICS8432-111
700MHZ/350MHZ
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in
Figure 6.
To calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
CCO
- 2V.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OH_MAX
)
Pd_L = [(V
OL_MAX
– (V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OL_MAX
)
For logic high, V
OUT
= V
OH_MAX
= V
CCO_MAX
– 1.0V
Using V
CCO_MAX
= 3.465, this results in V
OH_MAX
= 2.465V
For logic low, V
OUT
= V
OL_MAX
= V
CCO_MAX
– 1.7V
Using V
CCO_MAX
= 3.465, this results in V
OL_MAX
= 1.765V
Pd_H =[(2.465V - (3.465V - 2V))/50
] * (3.465V - 2.465V) = 20mW
Pd_L =[(1.765V - (3.465V - 2V))/50
] * (3.465V - 1.765V) = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
Q1
V
OUT
V
CCO
RL
50
V
CCO - 2V
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