參數(shù)資料
型號(hào): ICS845252AKILFT
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 14/17頁
文件大?。?/td> 0K
描述: IC CLK GENERATOR CML 32VFQFN
標(biāo)準(zhǔn)包裝: 2,500
系列: HiPerClockS™, FemtoClock™
類型: *
PLL: 帶旁路
輸入: LVCMOS,LVTTL,晶體
輸出: CML
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 無/是
頻率 - 最大: 312.5MHz
除法器/乘法器: 是/無
電源電壓: 2.375 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 32-VFQFPN 裸露焊盤(4x4)
包裝: 帶卷 (TR)
ICS845252AKI REVISION A SEPTEMBER 30, 2009
6
2009 Integrated Device Technology, Inc.
ICS845252I Data Sheet
FEMTOCLOCK CRYSTAL-TO-CML CLOCK GENERATOR
AC Characteristics
Table 6A. AC Characteristics, VDD = 3.3V±5%, TA = -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 1: fREF = 25 MHz.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Please refer to the phase noise plots.
Table 6B. AC Characteristics, VDD = 2.5V±5%, TA = -40°C to 85°C
For NOTES see Table 6A above.
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fOUT
Output Frequency; NOTE 1
FBSEL = 0, FSEL[1:0] = 00
312.5
MHz
FBSEL = 0, FSEL[1:0] = 01
156.25
MHz
FBSEL = 0, FSEL[1:0] = 10
125
MHz
FBSEL = 0, FSEL[1:0] = 11
62.5
MHz
FBSEL = 1, FSEL[1:0] = 00
250
MHz
FBSEL = 1, FSEL[1:0] = 01
125
MHz
FBSEL = 1, FSEL[1:0] = 10
100
MHz
FBSEL = 1, FSEL[1:0] = 11
50
MHz
tsk(o)
Output Skew; NOTE 1, 2, 3
60
ps
tjit()
RMS Phase Jitter (Random);
NOTE 4
FSEL = 0, 125MHz,
Integration Range: 1.875MHz – 20MHz
400
fs
FSEL = 0, 156.25MHz,
Integration Range: 1.875MHz – 20MHz
408
fs
tR / tF
Output Rise/Fall Time
20% to 80%
300
850
ps
odc
Output Duty Cycle
FBSEL[1:0]
≠ 10
48
52
%
FBSEL[1:0] = 10
46
54
%
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fOUT
Output Frequency; NOTE 1
FBSEL = 0, FSEL[1:0] = 00
312.5
MHz
FBSEL = 0, FSEL[1:0] = 01
156.25
MHz
FBSEL = 0, FSEL[1:0] = 10
125
MHz
FBSEL = 0, FSEL[1:0] = 11
62.5
MHz
FBSEL = 1, FSEL[1:0] = 00
250
MHz
FBSEL = 1, FSEL[1:0] = 01
125
MHz
FBSEL = 1, FSEL[1:0] = 10
100
MHz
FBSEL = 1, FSEL[1:0] = 11
50
MHz
tsk(o)
Output Skew; NOTE 1, 2, 3
60
ps
tjit()
RMS Phase Jitter (Random);
NOTE 4
FSEL = 0, 125MHz,
Integration Range: 1.875MHz – 20MHz
406
fs
FSEL = 0, 156.25MHz,
Integration Range: 1.875MHz – 20MHz
441
fs
tR / tF
Output Rise/Fall Time
20% to 80%
300
850
ps
odc
Output Duty Cycle
FBSEL[1:0]
≠ 10
48
52
%
FBSEL[1:0] = 10
46
54
%
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