參數(shù)資料
型號: ICS85222AM-01LFT
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘及定時
英文描述: LOW SKEW CLOCK DRIVER, PDSO8
封裝: 3.90 X 4.92 MM, 1.37 MM HEIGHT, LEAD FREE, MS-012, SOIC-8
文件頁數(shù): 12/13頁
文件大?。?/td> 262K
代理商: ICS85222AM-01LFT
85222AM-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 15, 2005
8
Integrated
Circuit
Systems, Inc.
ICS85222-01
DUAL LVCMOS / LVTTL-TO-
DIFFERENTIAL HSTL TRANSLATOR
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85222-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85222-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
DD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX = VDD_MAX * IDD_MAX = 3.465V * 35mA = 121.3mW
Power (outputs)
MAX = 82.34mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 82.34mW = 164.68mW
Total Power
_MAX (3.465V, with all outputs switching) = 121.3mW + 164.68mW = 285.98mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj =
θ
JA * Pd_total + TA
Tj = Junction Temperature
θ
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total device power dissipation (example calculation is in Section 1 above)
T
A = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
θ
JA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W per Table 5 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.286W * 103.3°C/W = 99.5°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
θθθθθ
JA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
153.3°C/W
128.5°C/W
115.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
112.7°C/W
103.3°C/W
97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 5. THERMAL RESISTANCE
θθθθθ
JA
FOR
8-PIN SOIC, FORCED CONVECTION
相關(guān)PDF資料
PDF描述
ICS85222AM-02T 85222 SERIES, LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
ICS85222AMLFT LOW SKEW CLOCK DRIVER, PDSO8
ICS85222AMLFT LOW SKEW CLOCK DRIVER, PDSO8
ICS8522AY-01LFT LOW SKEW CLOCK DRIVER, 17 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52
ICS8522AY-01LF LOW SKEW CLOCK DRIVER, 17 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52
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