參數(shù)資料
型號: ICS853013AMLFT
元件分類: 時鐘及定時
英文描述: 853013 SERIES, LOW SKEW CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
封裝: 7.50 X 12.80 MM, 2.30 MM HEIGHT, LEAD FREE, MS-013, MO-119, SOIC-20
文件頁數(shù): 4/17頁
文件大小: 448K
代理商: ICS853013AMLFT
853013AM
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 19, 2005
12
Integrated
Circuit
Systems, Inc.
ICS853013
LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO-
2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER
θθθθθ
JA
by Velocity (Linear Feet per Minute)
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853013.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS853013 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC = 5.25V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX = VCC_MAX * IEE_MAX = 5.25V * 60mA = 315mW
Power (outputs)
MAX = 30.94mW/Loaded Output pair
If all outputs are loaded, the total power is 6 * 30.94mW = 185.64mW
Total Power
_MAX (5.25V, with all outputs switching) = 315mW + 185.64mW = 500.64mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj =
θ
JA * Pd_total + TA
Tj = Junction Temperature
θ
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
θ
JA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 39.7°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.500W * 39.7°C/W = 104.85°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE
θθθθθ
JA
FOR
20-PIN SOIC, FORCED CONVECTION
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
83.2°C/W
65.7°C/W
57.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
46.2°C/W
39.7°C/W
36.8°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
相關(guān)PDF資料
PDF描述
ICS853013AMT 853013 SERIES, LOW SKEW CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
ICS853014AG LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
ICS853014AGLF LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
ICS853014BGLFT 853014 SERIES, LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
ICS853016AG 853016 SERIES, LOW SKEW CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
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