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參數(shù)資料
| 型號(hào)： | ICS853013AMT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 853013 SERIES, LOW SKEW CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封裝： | 7.50 X 12.80 MM, 2.30 MM HEIGHT, MS-013, MO-119, SOIC-20 |
| 文件頁數(shù)： | 5/18頁 |
| 文件大?。?/td> | 745K |
| 代理商： | ICS853013AMT |
ICS853013
LOW SKEW, DUAL,1-TO-3, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER
IDT / ICS 2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER
13
ICS853013AM REV. B FEBRUARY 7, 2008
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS853013.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS853013 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 5.25V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)MAX = VCC_MAX * IEE_MAX = 5.25V * 60mA = 315mW
Power (outputs)MAX = 30.94mW/Loaded Output pair
If all outputs are loaded, the total power is 6 * 30.94mW = 185.64mW
Total Power_MAX (3.8V, with all outputs switching) = 315mW + 185.64mW = 500.64mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj =
θ
JA * Pd_total + TA
Tj = Junction Temperature
θ
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
θ
JA must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 46.2°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.501W * 46.2°C/W = 108.1°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (single layer or multi-layer).
Table 6. Thermal Resistance θJA for 20 Lead SOIC Forced Convection
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
θ
JA by Velocity
Linear Feet per Minute
0200
500
Single-Layer PCB, JEDEC Standard Test Boards
83.2°C/W
65.7°C/W
57.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
46.2°C/W
39.7°C/W
36.8°C/W
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