參數(shù)資料
型號(hào)： ICS85354AK-01T
元件分類： 編、解碼器及復(fù)用、解復(fù)用
英文描述： 85354 SERIES, 2 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, QCC16
封裝： 3 X 3 MM, 0.95 MM HEIGHT, MO-220, VQFN-16
文件頁(yè)數(shù)： 17/18頁(yè)
文件大?。?/td> 231K
代理商： ICS85354AK-01T
85354AK-01
www.icst.com/products/hiperclocks.html
REV. A MARCH 17, 2006
8
Integrated
Circuit
Systems, Inc.
ICS85354-01
DUAL 2:1/1:2
DIFFERENTIAL-TO-LVPECL/ECL MULTIPLEXER
PRELIMINARY
ADDITIVE PHASE JITTER
Additive Phase Jitter at
622.08MHz = 0.05ps (typical)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
10
100
1k
10k
100k
1M
10M
100M
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is
called the dBc Phase Noise. This value is normally expressed
using a Phase noise plot and is most often the specified plot
in many applications. Phase noise is defined as the ratio of
the noise power present in a 1Hz band at a specified offset
from the fundamental frequency to the power value of the
fundamental. This ratio is expressed in decibels (dBm) or a
As with most timing specifications, phase noise measure-
ments have issues. The primary issue relates to the limita-
tions of the equipment. Often the noise floor of the equipment
is higher than the noise floor of the device. This is illustrated
ratio of the power in the 1Hz band to the power in the funda-
mental. When the required offset is specified, the phase noise
is called a dBc value, which simply means dBm at a specified
offset from the fundamental. By investigating jitter in the fre-
quency domain, we get a better understanding of its effects
on the desired application over the entire time record of the
signal. It is mathematically possible to calculate an expected
bit error rate given a phase noise plot.
above. The device meets the noise floor of what is shown, but
can actually be lower. The phase noise is dependant on the
input source and measurement equipment.
OFFSET FROM CARRIER FREQUENCY (HZ)
SSB
P
HASE
N
OISE
dB
c/H
Z
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