IDT / ICS LVCMOS/LVTTL ZERO DELAY CLOCK B" />
參數(shù)資料
型號: ICS86004BG-01LFT
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 10/11頁
文件大小: 0K
描述: IC CLK BUFFER ZD 1:4 16-TSSOP
標準包裝: 2,500
系列: HiPerClockS™
類型: 扇出配送,多路復(fù)用器,零延遲緩沖器
PLL: 帶旁路
輸入: LVCMOS,LVTTL
輸出: LVCMOS,LVTTL
電路數(shù): 1
比率 - 輸入:輸出: 1:4
差分 - 輸入:輸出: 無/無
頻率 - 最大: 250MHz
除法器/乘法器: 是/無
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 帶卷 (TR)
其它名稱: 86004BG-01LFT
IDT / ICS LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
8
ICS86004BG-01 REV. D JANUARY 19, 2009
ICS86004-01
62.5MHZ TO 250MHZ, 1:4 LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
APPLICATION INFORMATION
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. To achieve optimum jitter per-
formance, power supply isolation is required. The ICS86004-01
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
DD, VDDA and VDDO
should be individually connected to the power supply
plane through vias, and 0.01F bypass capacitors should be used
for each pin.
Figure 1 illustrates this for a generic V
DD pin and
also shows that V
DDA requires that an additional 10Ω resistor
along with a 10F bypass capacitor be connected to the V
DDA
pin.
POWER SUPPLY FILTERING TECHNIQUES
FIGURE 1. POWER SUPPLY FILTERING
INPUTS:
LVCMOS CONTROL PINS:
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional
protection. A 1k
Ω resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
LVCMOS OUTPUTS:
All unused LVCMOS output can be left floating. We recommend
that there is no trace attached.
FIGURE 2. ICS86004-01 SCHEMATIC EXAMPLE
SCHEMATIC EXAMPLE
Figure 2 shows a schematic example of using an ICS86004-01.
It is recommended to have one decouple capacitor per power
pin. Each decoupling capacitor should be located as close as
possible to the power pin. The low pass filter R7, C11 and C16
for clean analog supply should also be located as close to the
V
DDA pin as possible.
VDD
Ro ~ 7 Ohm
LVCMOS
R4
100
U1
ICS86004-01
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Q1
GND
Q0
F_SEL
VDD
CLK
GND
VDDA
PLL_SEL
FB_IN
MR
VDDO
Q3
GND
Q2
VDDO
VDD
R3
1K
C11
0.01u
R2
43
VDD
Zo = 50
R11
43
Serial Termination
VDD
R6
1K
Zo = 50
(U1-12)
VDD
C2
0.1uF
(U1-5)
Zo = 50
VDD
C16
10u
VDD=3.3V
R8
43
Parallel Termination
Zo = 50
R7
10
R1
43
VDD
C3
0.1uF
(U1-16)
C1
0.1uF
R5
100
VDD
VDDA
3.3V or 2.5V
10
Ω
10F
.01F
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