參數(shù)資料
型號: ICS86004BGLFT
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 6/10頁
文件大?。?/td> 0K
描述: IC CLK BUFFER ZD 1:4 16-TSSOP
標(biāo)準(zhǔn)包裝: 2,500
系列: HiPerClockS™
類型: 扇出配送,多路復(fù)用器,零延遲緩沖器
PLL: 帶旁路
輸入: LVCMOS,LVTTL
輸出: LVCMOS,LVTTL
電路數(shù): 1
比率 - 輸入:輸出: 1:4
差分 - 輸入:輸出: 無/無
頻率 - 最大: 62.5MHz
除法器/乘法器: 是/無
電源電壓: 2.375 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 帶卷 (TR)
其它名稱: 86004BGLFT
2005 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FMS6363 Rev. 1.0.4
5
FM
S6363
Low-
C
ost
,Three-
C
h
annel,6t
h
-O
rder,
H
igh-
D
e
finit
ion,
Video
Filt
er
D
river
Applications Information
Functional Description
The FMS6363 Low-Cost Video Filter (LCVF) provides
6dB gain from input to output. In addition, the input is
slightly offset to optimize the output driver performance.
The offset is held to the minimum required value to
decrease the standing DC current into the load. Typical
voltage levels are shown in Figure 8.
There will be a 280mV offset from the DC input level to
the DC output level.
Vout = 2 * Vin + 280mV
0.02V
0.32V
1.02V
VIN
0.15V
0.5V
0.85V
VIN
0.28V
0.88V
2.28V
Driven by:
DC-Coupled DAC Outputs o r
AC-Coupled and Clamped
Y, R, G, B, CV
VOUT
0.58V
1.28V
1.98V
Driven by:
DC-Coupled DAC Outputs
AC-Coupled and Biased
U, V, Pb, Pr, C
VOUT
Figure 8. Typical Voltage Levels
The FMS6363 provides an internal diode clamp to
support AC coupled input signals. If the input signal
does not go below ground, the input clamp does not
operate. This allows DAC outputs to directly drive the
FMS6363 without an AC coupling capacitor. The worst-
case sync tip compression due to the clamp does not
exceed 7mV. The input level set by the clamp,
combined with the internal DC offset, keeps the output
within its acceptable range. When the input is AC-
coupled, the diode clamp sets the sync tip (or lowest
voltage) just below ground.
For symmetric signals like C, U, V, Cb, Cr, Pb and Pr;
the average DC bias is fairly constant and the inputs
can be AC-coupled with the addition of a pull-up resistor
to set the DC input voltage. DAC outputs can also drive
these same signals without the AC coupling capacitor.
A conceptual illustration of the input clamp circuit is
shown in Figure 9.
YOUT
800k
Driver
YIN
0.65V
Figure 9. Input Clamp Circuit
I/O Configurations
For DC-coupled DAC drive with DC-coupled outputs,
use the configuration in Figure 10.
DVD or
STB
SoC
DAC
Output
75
Ω
LCVF
Clamp
Inactive
0V- 1.4V
Figure 10. DC-coupled Inputs and Outputs
Alternatively, if the DAC’s average DC output level
causes the signal to exceed the range of 0V to 1.4V, it
can be AC-coupled, as shown in Figure 11.
DVD or
STB
SoC
DAC
Output
75
Ω
LCVF
Clamp
Active
0.1
0V- 1.4V
Figure 11. AC-coupled Inputs, DC-coupled Outputs
When the FMS6363 is driven by an unknown external
source or a SCART with its own clamping circuitry the
inputs should be AC-coupled, shown in Figure 12.
75
Ω
LCVF
Clamp
Active
75
Ω
0.1
External Video
source must
be AC-coupled.
0V- 1.4V
Figure 12. SCART with DC-coupled Outputs
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