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參數(shù)資料
| 型號： | ICS87159AGLF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 4/17頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN 1-8 LVCMOS 56-TSSOP |
| 標準包裝： | 34 |
| 系列： | HiPerClockS™ |
| 類型： | 時鐘發(fā)生器 |
| PLL： | 無 |
| 輸入： | HCSL，LVDS，LVHSTL，LVPECL，SSTL |
| 輸出： | HCSL，LVCMOS，LVTTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:9 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 600MHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-TFSOP（0.240"，6.10mm 寬） |
| 供應商設備封裝： | 56-TSSOP |
| 包裝： | 管件 |
| 其它名稱： | 800-1966-5 87159AGLF ICS87159AGLF-ND |
87159AG
www.idt.com
REV. B JULY 25, 2010
12
ICS87159
1-TO-8 LVPECL-TO-HCSL
÷1, ÷2, ÷4 CLOCK GENERATOR
D2
B) Input with internal pull down resistor
D2
INPUT_DOWN
D1
INPUT_PU
RU
51K
VDD
RD
51K
VDD
A) Input with internal pull up resistor
LOGIC CONTROL INPUT
The logic input control signals are 3.3V LVCMOS compatible.
The logic control input contains ESD diodes and either pull-up
or pull-down resistor as shown in Figure 5. The data sheet pro-
vides pull-up or pull-down information for each input pin. Leav-
ing the input floating will set the control logic to default setting.
HCSL DRIVER TERMINATION
The HCSL is a differential constant current source driver. The
output current is set by control pins MULT_[1:0] and the value of
resistor Rref.
In the characteristic impedance of 50 Ohm environment, the
match load 50 Ohm resistors R4 and R5 are terminated at the
receiving end of the transmission line. The 33 Ohm series resis-
tor R6 and R7 should be located as close to the driver pins as
possible. For the clock traces that required very low skew should
have equal length.
Other general rules of high-speed digital design also should be
followed. Some check points are listed as follows:
-
Avoid sharp angles on the clock trace. Sharp angle turn
causes the characteristic impedance change on the
transmission lines.
-
Keep the clock trace on same layer. Whenever possible,
avoid any vias on the middle clock traces. Any via on
middle the trace can affect the trace characteristic
impedance and hence degrade signal quality.
-
There should be sufficient space between the clock traces
that have different frequencies to avoid cross talk.
-
No other signal trace is routed between the clock trace
pair.
-
Transmission line should not be routed across the split
plane on the adjacent layer.
To set logic high, the input pin connected directly to V
DD. To set
logic low, the control input connect directly to ground. For con-
trol signal source from the driver that has different power sup-
ply, a series current resistor of greater than 100 Ohm is required
for random power on sequence.
FIGURE 5. LOGIC INPUT CONTROLS
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| ICS87159AGLFT | 功能描述:IC CLOCK GEN 1-8 LVCMOS 56-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™ 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應商設備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| ICS871S1022EKLF | 制造商:Integrated Device Technology Inc 功能描述:IC FEMTOCLOCK LVPE 32VFQFN |
| ICS871S1022EKLFT | 制造商:Integrated Device Technology Inc 功能描述:IC FEMTOCLOCK LVPE 32VFQFN |
| ICS8725AM-21LF | 功能描述:IC CLOCK GEN ZD HSTL 20-SOIC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™ 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ICS8725AM-21LFT | 功能描述:IC CLOCK GEN ZD HSTL 20-SOIC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™ 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應商設備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
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