參數(shù)資料
型號(hào): ICS8741004AGLF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 4/19頁
文件大小: 0K
描述: IC PCI EXPRSS/JITT ATTEN 24TSSOP
標(biāo)準(zhǔn)包裝: 62
系列: HiPerClockS™, FemtoClock™, PCI Express® (PCIe)
類型: 扇出緩沖器(分配),漂移衰減器
PLL:
主要目的: PCI Express(PCIe)
輸入: HCSL,LVDS,LVHSTL,LVPECL,SSTL
輸出: LVDS
電路數(shù): 1
比率 - 輸入:輸出: 1:4
差分 - 輸入:輸出: 是/是
頻率 - 最大: 160MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 24-TSSOP
包裝: 管件
其它名稱: 800-2401-5
8741004AGLF
ICS8741004AGLF-ND
ICS8741004
DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS JITTER ATTENUATOR
IDT / ICS PCI EXPRESS JITTER ATTENUATOR
12
ICS8741004AG REV. AMAY 29, 2008
Recommendations for Unused Input and Output Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
resistor can be used.
Outputs:
Differential Outputs
All unused differential outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
LVDS Outputs
All unused LVDS output pairs can be either left floating or
terminated with 100
across. If they are left floating, we
recommend that there is no trace attached.
LVDS Driver Termination
A general LVDS interface is shown in Figure 4. In a 100
differential transmission line environment, LVDS drivers require a
matched load termination of 100
across near the receiver input.
For a multiple LVDS outputs buffer, if only partial outputs are used,
it is recommended to terminate the unused outputs.
Figure 4. Typical LVDS Driver Termination
3.3V
LVDS Driver
R1
100
+
3.3V
50
50
100
Differential Transmission Line
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