參數(shù)資料
型號: ICS8745BM-21LF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 7/19頁
文件大?。?/td> 0K
描述: IC CLK GEN ZD DIFF-LVDS 20-SOIC
標(biāo)準(zhǔn)包裝: 37
系列: HiPerClockS™
類型: 時鐘發(fā)生器
PLL: 帶旁路
輸入: HCSL,LVDS,LVHSTL,LVPECL,SSTL
輸出: LVDS
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 是/是
頻率 - 最大: 700MHz
除法器/乘法器: 是/是
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 20-SOIC
包裝: 管件
其它名稱: 800-1218
800-1218-5
800-1218-ND
8745BM-21LF
ICS8745BM-21 REVISION D JANUARY 25, 2010
15
2010 Integrated Device Technology, Inc.
ICS8745B-21 Data Sheet
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS8745B-21.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS8745B-21 is the sum of the core power plus the analog power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (125mA + 17mA) = 492mW
Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 59mA = 204mW
Total Power_MAX = 492mW + 204mW = 696mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj =
θ
JA * Pd_total + TA
Tj = Junction Temperature
θ
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
θ
JA must be used. Assuming a moderate air
flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 39.7°C/W per Table 7below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.696W * 39.7°C/W = 97.6°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance θJA for 20 Lead SOIC, Forced Convection
θ
JA vs. Air Flow
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
83.2°C/W
65.7°C/W
57.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
46.2°C/W
39.7°C/W
36.8°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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