參數(shù)資料
型號: ICS894D115AGI-04LF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 2/15頁
文件大小: 0K
描述: IC CLK/DATA RECOVERY 20-TSSOP
標準包裝: 74
系列: HiPerClockS™
類型: 時鐘和數(shù)據(jù)恢復(fù)(CDR),多路復(fù)用器
PLL:
主要目的: STM-1,STM-4
輸入: LVDS
輸出: LVDS
電路數(shù): 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 622.08MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 管件
其它名稱: 894D115AGI-04LF
ICS894D115I-04
OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE
IDT / ICS CLOCK/DATA RECOVERY DEVICE
10
ICS894D115AGI-04 REV. C OCTOBER 15, 2008
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter perform-
ance, power supply isolation is required. The ICS894D115I-04
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD and VDDA should
be individually connected to the power supply plane through vias,
and 0.01F bypass capacitors should be used for each pin. Figure
2 illustrates this for a generic VDD pin and also shows that VDDA
requires that an additional 10
resistor along with a 10F bypass
capacitor be connected to the VDDA pin.
Figure 2. Power Supply Filtering
Recommendations for Unused Input and Output Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
resistor can be used.
Outputs:
LVDS Outputs
All unused LVDS output pairs can be either left floating or
terminated with 100
across. If they are left floating, there should
be no trace attached.
3.3V LVDS Driver Termination
A general LVDS interface is shown in Figure 3. In a 100
differ-
ential transmission line environment, LVDS drivers require a
matched load termination of 100
across near the receiver input.
Figure 3. Typical LVDS Driver Termination
VDD
VDDA
3.3V
10
10F
.01F
3.3V
LVDS Driver
R1
100
+
3.3V
50
50
100
Differential Transmission Line
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