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參數(shù)資料
| 型號(hào)： | ICS894D115AGI-04LFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 8/15頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK/DATA RECOVERY 20-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | HiPerClockS™ |
| 類型： | 時(shí)鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | STM-1，STM-4 |
| 輸入： | LVDS |
| 輸出： | LVDS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 622.08MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 894D115AGI-04LFT |
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ICS894D115I-04
OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE
IDT / ICS CLOCK/DATA RECOVERY DEVICE
2
ICS894D115AGI-04 REV. C OCTOBER 15, 2008
Functional Description
The ICS894D115I-04 is designed to extract the clock from a
NRZ-coded STM-4 (OC-12/STS-12) or STM-1 (OC-3/STS-3) input
data signals. The output signals are the recovered clock and
retimed data signals. The device contains an integrated PLL for
clock generation and to lock the output clock to the input data
stream. The PLL attempts to lock to the reference clock input
(REF_CLK) in absence of the serial data stream or if it is forced to
by the control inputs LOCK_REFN or SD. The output clock
frequency is controlled by the STS12 input. The output frequency
is 622.08MHz in STM-4/OC-12/STS-12 mode and 155.52MHz in
STM-1/OC-3/STS-3 mode.
The ICS894D115I-04 will maintain an output (CLK_OUT/
nCLK_OUT) frequency deviation of less than ±500ppm with
respect to the REF_CLK reference frequency in a loss of signal
state (LOS). During the LOS state, the data outputs (DATA_OUT/
nDATA_OUT) are held at logic low state. An LOS state of the
ICS894D115I-04 is given when BYPASS is set to the logic low
state and either one of the SD or LOCK_REFN inputs are at a logic
low state. This will enable the use of the SD (signal detect) and the
LOCK_REFN (lock-to-reference) inputs to accept loss of signal
status information from electro-optical receivers. Please refer to
Figure 1, “Signal Detect/PLL Bypass Operation Control Diagram”,
for details.
The lock detect output (LOCK_DET) can be used to monitor the
operating state of the clock/data recovery circuit. LOCK_DET is set
to logic low level when the internal oscillator of the PLL and the
reference clock (REF_CLK) deviate from each other by more than
500ppm, or when the CDR is forced to lock the REF_CLK input by
the LOCK_REFN or SD control input. LOCK_DET is set to high
when the PLL is locked to the input data stream and indicates valid
clock and data output signals.
The BYPASS pin should be set to logic low state in all applications.
BYPASS set to logic high state is used during factory test. In
BYPASS mode (BYPASS and STS12 are at logic high state), the
internal PLL is bypassed and the inverted REF_CLK input signal is
output at CLK_OUT/nCLK_OUT.
Figure 1. Signal Detect/PLL BYPASS Operation Control Diagram
LOS
(on-chip)
DATA_OUT
nDATA_OUT
CLK_OUT
nCLK_OUT
STS12
BYPASS
DATA_IN
nDATA_IN
PLL Clock
(on-chip)
SD
LOCK_REFN
REF_CLK
0
1
Pullup/Pulldown
Pulldown
Pullup
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