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參數(shù)資料
| 型號： | ICS90C64A-903V |
| 英文描述： | Video/Graphics Clock Generator |
| 中文描述： | 視頻/圖形時鐘發(fā)生器 |
| 文件頁數(shù)： | 2/10頁 |
| 文件大?。?/td> | 360K |
| 代理商： | ICS90C64A-903V |
ICS90C65 VGA Interface
The
ICS90C65
has two system interfaces: System Bus and
VGA Controller, as well as other programmable inputs. Figure
1 shows how the Integrated Circuit Systems’s VGA Clock
ICS90C65
is connected to a VGA controller. Western Digital
Imaging VGA controllers normally have a status bit that indi-
cates to the VGA controller that it is working with a clock chip.
When working with a clock chip the VGA controller changes
two of its clock inputs to outputs. They are
theVCLK1/VCSLD/VCSEL and VCLK2/VCSEL/VCSELH
outputs and they are used to select the required video frequency.
Figure 1
When the power-down capabilities are used, the control signal
for PWRDN is normally held in one of a group of latches. If
the power-down function is not to be used,
PWRDN must be
tied to V
DD
, otherwise the internal pull-down will place the chip
in the power-down mode.
VSEL0
14.318
MHz
SD3
SD2
pull-up at reset
and PR15(5)=0
AMD(3)
VCKIN
MCLK
VCSEL
VCS
ICS90C65
WD90C26
LATCH
VSEL1
VSEL2
VCLK
MC
SELEN
CLK1
PWRDN
ICS90C65
2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS90C64A-907M | Video/Graphics Clock Generator |
| ICS90C64A-907N | Video/Graphics Clock Generator |
| ICS90C64A-907V | Video/Graphics Clock Generator |
| ICS90C64A-909M | Video/Graphics Clock Generator |
| ICS90C64A-909N | Video/Graphics Clock Generator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS90C64A-907M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video/Graphics Clock Generator |
| ICS90C64A-907N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video/Graphics Clock Generator |
| ICS90C64A-907V | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video/Graphics Clock Generator |
| ICS90C64A-909M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video/Graphics Clock Generator |
| ICS90C64A-909N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video/Graphics Clock Generator |
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