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參數(shù)資料
| 型號： | ICS90C64A-XXXV |
| 英文描述： | Peripheral IC |
| 中文描述： | 外圍芯片 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大小： | 360K |
| 代理商： | ICS90C64A-XXXV |
Inputs from VGA Controller
The VGA controller input to the
ICS90C65
is:
SELEN
The
ICS90C65
is programmed to generate different video
clock frequencies using the inputs of VSEL0, VSEL1, VSEL2,
and VSEL3. The signals VSEL2 and VSEL3 may be supplied
by the VGA controller as is the case in Western Digital Imaging
VGA controllers. The inputs VSEL0-1 are latched with the
signal SELEN. The SELEN input should be an active low
pulse. This active low pulse is generated in Western Digital
Imaging VGA controllers during I/O writes to internal register
3C2h.
Note: Only VSEL0 and VSEL1 are latched with signal SELEN.
Outputs to VGA Controller
The outputs from the
ICS90C65
to the VGA controller are:
MCLK
VCLK
MCLK and VCLK are the two clock outputs to the VGA
controller.
User-Definable Inputs
The user definable inputs are:
EXTCLK
VLCKE, MCLKE
MSELO-2
VSEL2, VSEL3
PWRDN
EXTCLK is an additional input that may be internally routed
to the VCLK output. This additional input is useful for support-
ing modes that require frequencies not provided by the
ICS90C65
or for use during board test.
VCLKE and MCLKE are the output enable signals for VCLK
and MCLK. When low the respective output is tristated.
MSEL0-2 are the memory clock (MCLK) select lines. Ta-
ble 1-2 shows how MCLK frequencies are selected. All signals
in this group have internal pull-up resistors.
VSEL2 and VSEL3 are video clock (VCLK) select lines that
can select additional VCLK frequencies. See Table 1-1.
VSEL2 and VSEL3 have internal pull-ups.
PWRDN can place the
ICS90C65
in a power-down mode
which drops its supply current requirement below 1 microamp.
When placed in this mode, the digital inputs may be either high
or low or floating without causing an increase in the
ICS90C65
supply current.
The PWRDN pin must be low (It has an internal pull-down.)
in order to place the device in its low power state. The output
pins (VCLK and MCLK) are driven high by the
ICS90C65
when it is in its low power state.
If CLKI is being driven by an external source, it may be driven
low or high without a power penalty. If CLKI is at an interme-
diate voltage (V
SS
+0.5 < V
IN
<V
DD
-0.5), there will be a small
increase in supply current. If CLKI is driven at 14.318 MHz
while the chip is in power-down, the
ICS90C65
supply current
will increase to approximately 1.2 mA.
The SELEN (pin 6) may be used to guard against inadvertent
frequency changes during power-down/powerup sequences.
By holding the SELEN low during power-down and power-up
sequences, the
ICS90C65
will retain the most recent video
frequency selection.
Analog Filters
The analog filters are integral to the
ICS90C65
device. No
external components are required. This feature reduces PC
board space requirements and component costs. Phase-jitter is
reduced as externally-generated noise cannot easily influence
the phase-locked loop filter.
System Bus Inputs
The system bus inputs are:
CLKI
VSEL0
VSEL1
The
ICS90C65
uses the system bus 14.318 MHz clock as a
reference to generate all its frequencies for both video and
memory clocks. Data lines D2 and D3 are commonly used as
inputs to VSEL0 and VSEL1 for video frequency selection.
ICS90C65
3
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS90C64M | Video/Graphics Clock Generator |
| ICS90C64N | Video/Graphics Clock Generator |
| ICS90C64V | Video/Graphics Clock Generator |
| ICS90C65-951M | Video/Graphics Clock Generator |
| ICS90C65-951N | Video/Graphics Clock Generator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS90C64M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video/Graphics Clock Generator |
| ICS90C64N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video/Graphics Clock Generator |
| ICS90C64V | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video/Graphics Clock Generator |
| ICS90C65 | 制造商:ICS 制造商全稱:ICS 功能描述:Dual Voltage Video/Memory Clock Generator |
| ICS90C65-951M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video/Graphics Clock Generator |
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